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AK4561 Datasheet, PDF (45/48 Pages) Asahi Kasei Microsystems – 16bit CODEC with built-in ALC and MIC/HP-Amp | |||
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4561]
n FADEIN Mode
In FADEIN Mode, the IPGA value is increased at the value set by FDATT when FDIN bit changes from â0â to â1â.
The update period can be set by FDTM1-0 bits. The FADEIN Mode is always detected by the zero crossing operation.
This operation is kept over the REF value or until the limiter operation at once. If the limiter operation is done during
FADAIN cycle, the FADEIN operation becomes the ALC operation.
NOTE: When FDIN and FDOUT bits are â1â, FDOUT operation is enabled.
IPGA Ouput
ALC bit
FDIN bit
(5)
(1) (2)
(3)
(4)
Figure 33. Example for controlling sequence in FADEIN operation
(1) WR (ALC = FDIN = â0â): The ALC operation is disabled. To start the FADEIN operation, FDIN bit is written in â0â.
(2) WR (IPGA = âMUTEâ): The IPGA output is muted.
(3) WR (ALC = FDIN = â1â): The FADEIN operation starts. The IPGA changes from the MUTE state to the FADEIN
operation.
(4) The FADEIN operation is done until the limiter detection level (LMTH) or the reference level (REF6-0). After
completing the FADEIN operation, the AK4561 becomes the ALC operation.
(5) FADEIN time can be set by FDTM1-0 and FDATT bits
E.g. FDTM1-0 = 32ms, FDATT = 1step
(96 x FDTM1-0) / FDATT = 96 x 32ms / 1 = 3.07s
Rev. 0.9
- 45 -
2000/09
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