AK4561 Datasheet, PDF (37/48 Pages) Asahi Kasei Microsystems – 16bit CODEC with built-in ALC and MIC/HP-Amp

ASAHI KASEI
AKM CONFIDENTIAL
[AK4561]
n Digital Delay Circuit
When DLYE bit is “1”, digital data (L1 and R1) of ADC can be delayed to a maximum 90tap (DLY6-0 bits) by a
resolution of 1/64fs (=3µs@fs=48kHz). The coefficient value subtracted from the opposite channel is set by COE3-0 bit.
When DLYE bit is “0”, the digital delay circuit is powered-down.
L2 = L1 – (ATT x (Delay x R1))
R2 = R1 – (ATT x (Delay x L1))
L1
DLY6- 0bit
R1
Delay
Delay
COE3- 0 bit
ATT
L2
ATT
R2
Figure 25. Digital Delay Circuit
DLYE, DLY6-0 and COE3-0 bits should be changed after ADC is powered-down. During the ADC is normal operation,
pop noise may occur by changing these bits. The following sentences are an example of changing these bits.
1. Powered-down ADC (PM2 bit = “0”)
2. Change DLYE, DLY6-0, COE3-0 bit
3. The power-down of ADC is released (PM2 bit = “1”)
Then ADC starts initialization cycle.
n Comparator Output
The input DC voltage form VTH pin is compared with analog output from HPF-Amp. COMP pin goes “H” when either
Lch or Rch of analog output exceeds threshold level, if it does not exceed the threshold level, COMP pin goes “L”.
This threshold level can be set by the input DC voltage from VTH pin. VTH pin should be supplied to DC voltage
(threshold of negative) divided by a resistor between MIC_B pin and MVSS pin. VTH pin can be supplied until minimum
(MVCM – MVDD x 0.35). For example, the input voltage of VTH pin is 0.4V when MVDD is 2.8V. The threshold of
positive side is converted by internal inverting amplifier.
Rev. 0.9
- 37 -
2000/09