AK4561 Datasheet, PDF (15/48 Pages) Asahi Kasei Microsystems – 16bit CODEC with built-in ALC and MIC/HP-Amp

ASAHI KASEI
AKM CONFIDENTIAL
[AK4561]
OPERATION OVERVIEW
n System Clock
The clock which are required to operate are MCLK (256fs/384fs), LRCK (fs), BCLK (32fs∼). The master clock (MCLK)
should be synchronized with LRCK but the phase is free of care.
The MCLK can be input 256fs or 384fs. When 384fs is input, the internal master clock is divided into 2/3 automatically.
* fs is sampling frequency.
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4561 may
occur click noise. In case of DAC, click noise is avoided by setting the inputs to “0”.
All external clocks (MCLK, BCLK and LRCK) should always be present. If these clocks are not provided, the AK4561
may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If
the external clocks are not present, the AK4561 should be in the power-down mode. (Refer to the “Power Management
Mode”.)
n System Reset
AK4561 should be reset once by bringing PD pin “L” upon power-up. After the system reset operation, the all internal
AK4561 registers become initial value.
Initializing cycle is 8224/fs=171.3ms@fs=48kHz. During initializing cycle, the ADC digital data outputs of both
channels are forced to a 2's compliment, “0”. Output data of ADC settles data equivalent for analog input signal after
initializing cycle. This cycle is not for DAC.
As a normal initializing cycle may not be executed, nothing writes at address 02H during initializing cycle.
n Digital High Pass Filter
The ADC has HPF for the DC offset cancel. The cut-off frequency of HPF is 3.7Hz (@fs=48kHz) and it is -0.15dB at
22Hz. It also scales with the sampling frequency (fs).
Rev. 0.9
- 15 -
2000/09