AK8826VN Datasheet, PDF (44/157 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

(1) Case of 525i /625i Data Input
[AK8826VN]
Y/Cb/Cr multiplexed data synchronized to 27MHz clock fed into CLKIN-pin are input.
When EAV-Decoding mode, the timing signal is extracted from data stream. After extracting sync-timing, the Y/Cb/Cr data are
proceeded into Y-process block and Cb/Cr -process block. In case of H/V Slave operation mode, it is same way as EAV sync
mode.
As shown in the block diagram,
Y data proceeded by x4 over-sampling filter is added the Sync-timing signal after pass through the delay adjustment block.
Cb/Cr data proceeded by x8 over-sampling filter are processed by delay adjustment block. These data are passed to the DAC
with 54MHz Clock rate.
8-bit or 16-bit
Cb/Y/Cr
27MHz
Synchronization Timing
EAV
Decoder
MUX
YData[9:0]
DEMUX
Level ^CBData[9:0]
Conversion
CRData[9:0]
4:2:2
to
4:4:4
Interpolation
LPF-E
x2
Interpolation
LPF-D
x2
Interpolation
LPF-F
x2
Interpolation
LPF-G
x2
Interpolation
LPF-H
Input Formatter
13.5MHz
27MHz
SYNC Form
Delay
DAC
Delay DAC
Delay
DAC
54MHz
Synchronization Mode
Fig. 36 525i/625i mode Block Diagram
x4 Over-sampling Filter for Y-data (Luminance Data)
10
0
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0
-10
-20
-30
-40
-50
-60
Frequency[MHz]
Fig. 37ç
x8 Over-Sampling Filter for Cb/Cr-Data (Color Data)
ç
10
0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
-10
-20
-30
-40
-50
-60
Frequency[MHz]
MS0972-E-01
Fig. 39
44
0.200
0.000
0.00 0.75 1.50 2.25 3.00 3.75 4.50 5.25 6.00 6.75
-0.200
-0.400
-0.600
-0.800
-1.000
Frequncy[MHz]
Fig. 38
2008/12