AK8826VN Datasheet, PDF(31/157 Page) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

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AK8826VN Datasheet, PDF (31/157 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

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[AK8826VN]

(1) YCbCr 8bit Data Input Format

In case of 525i / 625i Data Input, this forma is used. Data clock is 27MHz.

DATA7-DATA0 pins are used as Data Input pins. The order of YCbCr data should be fed Cb[7:0] / Y[7:0] / Cr[7:0] / Y[7:0].

Yn / Cbn / Crn means Y[n] / Cb[n] / Cr[n] in following table.

D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

-

-

-

-

-

-

-

-

-

- Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0

Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0

D17 - D0 corresponds to DATA17 - DATA0 pins

The Register setting is defined as following table.

[I/O Data Fromat Register] Setting

INPFMT[1:0]-bit

DTFMT-bit

Note

00

0

8bit YCbCr Data Input

Ã§

Output signal is set CONVMOD[1:0]-bit of I/O Data Format Register (R/W) [Sub Address 0x0B] and HD Mode Register

(R/W) [Sub Address 0x00] or SD Block Control Register (R/W) [Sub Address 0x11]

CLKIN

(27MHz)

DATA[7:0] Cb Y ÅÅÅ ÅÅÅ Cbn Y2n Crn Y2n+1 Cbn+1 Y2n+2 Crn+1 Y2n+3 Cbn+2 Y2n+4 Crn+2 ÅÅÅ ÅÅÅ

Fig. 24

MS0972-E-01

31

2008/12

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