AK8826VN Datasheet, PDF (125/157 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

HDYPBPR Delay Control Register (R/W) [Sub Address 0x02]ç
[Component Video Encoder]
Delay amounts of Y signal and Pb / Pr signals are set.
Sub Address 0x02
bit 7
bit 6
Reserved PBPRDLY2
0
0
bit 5
PBPRDLY1
0
bit 4
bit 3
PBPRDLY0 Reserved
Default Value
0
0
[AK8826VN]
Default Value 0x00
bit 2
bit 1
bit 0
HDYDELAY2 HDYDEALY1 HDYDELAY0
0
0
0
HDYPBPR Delay Control Register (R/W) [Sub Address 0x02]
BIT Register Name
R/W
Definition
Luminance signal delay amount is set. It is a delay from SYNC
signal.
Delay amount is set based on 27 MHz clock in 480i / p modes,
and 74.25 MHz in 1080i / 720p modes.
[ HDYDELAY2 : YDELAY1 ] - bit
000 : delay amount 0
bit 0 HDYDELAY0
~
~
bit 2 HDYDELAY2
HDY Delay Set bits
001: 1 CLK time is delayed.
R/W _{010: 2 CLK time is delayed.}
011: 3 CLK time is delayed.
bit 3 Reserved
bit 4 PBPRDLY0
~
~
bit 6 PBPRDLY2
bit 7 Reserved
Reserved bit
C Delay Set bits
Reserved bit
111: advance 1 CLK time to output.
110: advance 2 CLK time to output.
101: advance 3 CLK time to output.
100 : reserved
R/W Reserved, write “0 “.
Chroma signal delay amount is set. It is a delay from Luminance
signal.
Delay amount is set, based on 27 MHz clock in 480i/p modes, and
74.25 MHz in 1080i / 720p modes.
Both Pb / Pr are delayed by same amount by Delay Amount
setting.
[ PBPRDLY2 : PBPRDLY0 ] – bit
R/W
000: delay amount 0
001: 1 CLK time is delayed.
010: 2 CLK time is delayed.
011: 3 CLK time is delayed.
111: advance 1 CLK time to output.
110: advance 2 CLK time to output.
101: advance 3 CLK time to output.
100: reserved
R/W Reserved, write “0 “.
MS0972-E-01
125
2008/12