AK8826VN Datasheet, PDF (28/157 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

[AK8826VN]
■ Clock
Input Clock is determined by output signal. The relation between input Clock and the output signal is defined as following table.
Input Clock
NTSC/PAL
Component Video Encoder
Composite Video Encoder
mode
High Speed Video DAC mode
mode
D1, D2
D3, D4
Input Clock to CLKIN pin
27MHz
27MHz
74.25MHz 54MHz (max)
DAC operation clock rate
27MHz
54MHz
148.5MHz Clock to CLKIN pin
Internal PLL status
OFF
ON
ON
OFF
D1 = 480i/576i(525i/625i), D2 = 480p/576p (525p/625p), D3 = 1080i (1125i), D4 = 720p (750p)
In case of switching clock, PLLPDN-bit of Powerdown Mode Register (R/W) [Sub Address 0x06] should be “0”.
■ Internal PLL
AK8826 has x2 PLL.
In case of Component Video Encoder mode, PLL should be on.
In time to switch clock rate, PLLPDN-bit should be “0”.
Powerdown Mode Register
Sub Address 0x06 < HD Block >
bit 7
bit 6
bit 5
Reserved
Reserved
Reserved
bit 4
Reserved
bit 3
Reserved
bit 2
PLLPDN
Default Value 0x00
bit 1
bit 0
SLPEN1
SLPEN0
PLLPDN
0
1
PLL is Power Down
Function
PLL is working.
Set PLLPDN=1, in case of Component Video Encoder mode.
■ Reset
(1) Component Video Encoder Block and High Speed DAC Block, and Serial Interface Block are reset with making
PDN-pin = Low. It is not necessary to input clock to CLKIN pin.
(2) Composite Video Encoder Block.
Composite Video Encoder Block is reset under the condition of DTRSTN-bit =”0” of DAC Control Register(R/W) [Sub
Address 0x0D] with clock input to CLKIN-pin. It should be keep DTSTN-bit = “0” at least 100 clock count.
DAC Control Register
Sub Address 0x0D
bit 7
bit 6
Reserved
Reserved
bit 5
OLVL
bit 4
DTRSTN
bit 3
CVBSSEL
bit 2
DAC3EN
After Reset all register values become default value, and Video DAC output pins become Hi-z.
default Value 0x00
bit 1
bit 0
DAC2EN
DAC1EN
MS0972-E-01
28
2008/12