AK8826VN Datasheet, PDF (32/157 Pages) Asahi Kasei Microsystems – HD/SD Multi Format Video Encoder with 3ch DAC

[AK8826VN]
(2) YCbCr 16bit Data Input Format
In case of 525i / 625i / 525P / 625P / 1080i / 720P Data input, this format is used.
The relation between input data format and Input clock rate to CLKIN pin are relation as follows,
525i / 625i / 525p / 625p : 27MHz
1080i / 720p / : 74.25MHz
DATA15-DATA0 pins are used as Data Input pins.
Yn / Cbn / Crn means Y[n] / Cb[n] / Cr[n] in following table.
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
-
-
Cb7
Cr7
Cb6
Cr6
Cb5
Cr5
Cb4
Cr4
Cb3
Cr3
Cb2
Cr2
Cb1
Cr1
Cb0
Cr0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
D17 - D0 corresponds to DATA17 - DATA0 pins
The Register setting is defined as following table.
[I/O Data Fromat Register] Setting
INPFMT[1:0]-bit
DTFMT-bit
01
0
Note
16bit YCbCr Data Input
Output signal is set CONVMOD[1:0]-bit of I/O Data Format Register (R/W) [Sub Address 0x0B] and HD Mode Register
(R/W) [Sub Address 0x00] or SD Block Control Register (R/W) [Sub Address 0x11]
(2-1) 525i / 625i Data input
CLKIN
(27MHz)
Data[7:0]
Y₀
Y₁
Y₂
Y₃
ŋŋŋ
Y_2n
Y_2n+1
Y_2n+2
ŋŋŋ
Data[15:8]
Cb0
Cr₀
Cb₁
Cr₁
ŋŋŋ
Cb_n
Cr_n
Cb_n+1
ŋŋŋ
Fig. 25
(2-2) 525P / 625P / 1080i / 720P Data input
CLKIN
(27 or 74.25MHz)
Data[7:0]
Y₀ Y₁ Y₂ Y₃ ŋŋŋ ŋŋŋ ŋŋŋ ŋŋŋ Y_2n Y_2n+1 Y_2n+2 Y_2n+3 Y_2n+4 Y_2n+5 ŋŋŋ ŋŋŋ ŋŋŋ
Data[15:8]
Cb0 Cr₀ Cb₁ Cr₁ Cb₂ Cr_{2 ŋŋŋ ŋŋŋ} Cb_n Cr_n Cb_n+1 Cr_n+1 Cb_n+2 Cr_{n+2 ŋŋŋ ŋŋŋ ŋŋŋ}
Fig. 26
MS0972-E-01
32
2008/12