AK8853XQ Datasheet, PDF (4/70 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8853XQ/ VN]
3. Pin functions
Pin
No.
Symbol P/S¹ I/O²
Description
1 VRN
A
O
Internal reference negative voltage pin for AD converter.
Connect to AVSS via ≥0.1 µF ceramic capacitor.
2 AIN3
A
I
Analog video signal input pin. Connect via 0.033 µF capacitor and
voltage-splitting resistors as shown in Sec. 11.
3 VRP
A
O
Internal reference positive voltage pin for AD converter.
Connect to AVSS via ≥0.1 µF ceramic capacitor.
4 AIN2
A
I
Analog video signal input pin. Connect via 0.033 µF capacitor and
voltage-splitting resistors as shown in Sec. 11.
5 AVSS
A G Analog ground pin.
6 AVDD
A P Analog power supply pin.
7 AIN1
A
I
Analog video signal input pin. Connect via 0.033 µF capacitor and
voltage-splitting resistors as shown in Sec. 11.
8 AVSS
A G Analog ground pin.
9 DVDD
D P Digital power supply pin.
10 DVSS
D G Digital ground pin.
11 NSIG
Shows status of synchronization with input signal.
P1
O
Low: Signal present (synchronized).
High: Signal not present or not synchronized.
See Table below for relation of output to OE, PDN, RSTN pin status.
12
DVALID_
F
DVALID/FIELD signal output pin.
P1
O _{DVALID and FIELD output signals switched by register setting.}
(I/O) ^{Used as I/O pin in Test Mode.}
See Table below for relation of output to OE, PDN, RSTN pin status.
13 VD_F
Vertical timing/ field timing signal output pin.
P1 O VD and FIELD output signals switched by register setting.
See Table below for relation of output to OE, PDN, RSTN pin status.
14 HD
O ^{Horizontal timing signal output pin.}
P1
(I/O)
Used as I/O pin in Test Mode.
See Table below for relation of output to OE, PDN, RSTN pin status.
15 DATA7
O ^{Data output pin. (MSB)}
P1
Used as I/O pin in Test Mode.
(I/O) _{See Table below for relation of output to OE, PDN, RSTN pin status.}
16 DATA6
O ^{Data output pin.}
P1
Used as I/O pin in Test Mode.
(I/O) _{See Table below for relation of output to OE, PDN, RSTN pin status.}
17 DATA5
O ^{Data output pin.}
P1
Used as I/O pin in Test Mode.
(I/O) _{See Table below for relation of output to OE, PDN, RSTN pin status.}
18 DVSS
D G Digital ground pin.
19 DTCLK
Data clock output pin.
P1 O Approx. 27 MHz clock output.
See Table below for relation of output to OE, PDN, RSTN pin status.
20 PVDD1
P1 P I/O power supply pin.
21 DATA4
O ^{Data output pin.}
P1
Used as I/O pin in Test Mode.
(I/O) _{See Table below for relation of output to OE, PDN, RSTN pin status.}
1_{Power supply: A, AVDD; D, DVDD; P1, PVDD1; P2, PVDD2.}
2_{Input/Output: O, output pin; I, intput pin; I/O, input/output pin; P, power supply pin;}
G, ground connection pin.
Rev-E-00
4
2008/01