AK8853XQ Datasheet, PDF (30/70 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8853XQ/ VN]
The AK8853 outputs the following signals from the HD, VD_F, and DVALID_F pins, and the indicated
VD_F and DVALID_F output signals can also be selected via the register settings shown below.
Timing signal output pin
HD
VD_F
DVALID_F
525-line
Low for 4.7 µs at 15.734 kHz interval
VD
Low during lines 4~6
and 266.5~269.5
625-line
Low for 4.7 µs at 15.625 kHz interval
Low during lines 1~3.5
and 313.5~315
FIELD
ODD-Field: Low; EVEN-Field: High
DVALID
Active-Low
VFDSEL[1:0]-bits: Settings for VD/FIELD/DVALID selection
VFDSEL[1:0]-bits
VD_F pin
Pin output
DVALID_F pin
[00]
VD signal
DVALID signal
[01]
VD signal
Field signal
[10]
Field signal
DVALID signal
[11]
Reserved
Reserved
Output timing with 525-line input
CVBS
523 524
HD
VD
FIELD
525 1
EVEN
2
3
4
5
6
7
8
9
10
11
ODD
CVBS
HDç
VDç
FIELD
261 262 263 264 265 266 267 268 269 270 271 272 273 274
ODD
EVEN
Output timing with 625-line input
CVBS
620 621 622 623 624 625
1
2
3
4
5
6
7
8
HD
VD
FIELD
EVEN
ODD
CVBS
HD
VD
FIELD
308 309 310 311 312 313 314 315 316 317 318 319 320 321
ODD
EVEN
The output signal polarities of the DTCLK, HD, VD_F and DVALID_F pins can be reversed via “Output
Control Register” and “Control 0 Register” settings.
Rev-E-00
30
2008/01