AK8853XQ Datasheet, PDF (26/70 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

[AK8853XQ/ VN]
7.12 Digital Pixel Interpolator
The digital pixel interpolator of the AK8853 aligns vertical pixel positions in both frame-lock and
fixed-clock operating modes. The pixel interpolator can be set to ON or OFF via the register. With a
register setting of AUTO, the pixel interpolator is OFF or ON depending on the clock mode, as follows.
Line-locked clock mode
Frame-locked clock mode
Fixed-clock mode
OFF
ON
ON
INTPOL[1:0]-bits: Settings for pixel interpolator operation
INTPOL[1:0]-bits
Interpolator operation
[00]
Auto
[01]
ON
[10]
OFF
[11]
Reserved
Notes
Dependent on clock mode.
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7.13 Clock generation
The AK8853 operates in the following three clock modes.
1. Line-locked clock mode
The “line-locked clock” is generated by PLL using the horizontal sync signal within the input
signal. If no input signal is present, the AK8853 will switch from this mode to fixed-clock mode.
2. Frame-locked mode
The “frame-locked clock” is generated by PLL using the vertical sync signal within the input
signal. If no input signal is present, the AK8853 will switch from this mode to fixed-clock mode.
3. Fixed-clock mode
No PLL control is applied in this mode, which is enabled only when either it is set via the register
or no input signal is present. In this mode, data capture cannot be performed in EAV (end
active video), and must be performed in SAV (start active video) format. The number of pixels
per line is not guaranteed in this mode, but data guarantee is performed in the interval from SAV
to EAV.
The AK8853 transition function automatically switches among the above modes and selects the optimum
one, and when no input signal is present switches to the fixed-clock mode.
In the line-locked and frame-locked clock modes, the clock is synchronized with the input signal and the
output is thus ITU-R BT.656 compliant. It should be noted, however, that ITU-R BT.656-compliant
output may not be possible with low-quality input signals.
It should also be noted that in the fixed-clock mode the sample number will be insufficient for ITU-R
BT.656 compliance, due to non-synchronization of the input data.
CLKMODE[1:0]-bits: Settings for selection of clock generation mode
CLKMODE[1:0]-bits
Clock generation mode
[00]
Automatic
[01]
Line-locked
[10]
Frame-locked
[11]
Fixed-clock
Notes
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Rev-E-00
26
2008/01