AME9003 Datasheet, PDF (28/39 Pages) Asahi Kasei Microsystems – CCFL Backlight Controller

AME, Inc.
AME9003
Preliminary
CCFL Backlight Controller
Application Component Description
Figure 18 shows one typical application circuit for driv-
ing 4 tubes. Similar component designations are used
on similar components both in figure 2 and Figure 18 as
well as throughout this application note.
R1 - Weak pull up for the chip enable (CE) pin. The
voltage at CE will normally rise to 5 volts for a 12V
supply. Pull down on the CE node to disable the chip
and put it into a zero Idd mode. If the user wishes to
drive node CE with 3.3 or 5.5 volt logic then R1 is not
necessary
C1 - This capacitor acts to de-bounce the CE pin and
to slow the turn on time when using R1 to pull up CE.
This can be useful when the battery power is discon-
nected from the circuit in order to turn the circuit off,
when the battery is reconnected the chip does not
immediately turn on which allows the battery voltage
to stabilize before switching starts. If the user is ac-
tively driving the CE pin then the C1 capacitor may not
be necessary.
R3 - This resistor connected to the RDELTA pin deter-
mines how much the oscillator frequency will change
with battery voltage. The relation, which is found ear-
lier in the text, is:
Delta frequency (Hz) = 3.44e8 * (5 - V(FCOMP)) / R3
C2 - This 1uF capacitor bypasses and stabilizes the
internal reference
C3, C31 - These two capacitors determine the length
of the blanking interval at the beginning of every dim-
ming cycle. At the end of every dimming cycle these
capacitors are discharged to VSS then allowed to
charge up at a rate controlled by its internal current
source and the values of C3 and C31. When the volt-
age on pin SSC crosses 3 volts the blanking interval is
over and all fault checks are enabled. The charging
current out of pin SSC is normally 140uA but for the
very first cycle after the chip is enabled the current is
only 1.5uA. During the first cycle of operation one
side of C31 is tied to VSS through the SSC1ST pin.
This means that during the first cycle the effective ca-
pacitance on the SSC pin is C3 + C31. For subse-
quent cycles the SSC1ST pin reverts to a high imped-
ance state that effectively removes C31 from the cir-
cuit. The larger effective capacitor value plus the lower
charging current (1.5uA) determines the duration of
the intial start up period (nominally 1 second) and is
given by the relation:
28 _{T(seconds) =( C3+C31) * (3volts) / (1.5e-6amps)}
And for subsequent dimming cycles the blanking in-
terval is:
T(seconds) = (C3) * (3volts) / (140e-6amps)
R2 - R2 sets the frequency of the oscillator that drives
the FETs. The relation between R2 and frequency,
that was found previously in the text, is:
Frequency (Hz) = 2.8e9/R2
R2 = 56K yields approximately 50khz
Note: that this is the frequency of the NMOS(Q3) gate drive.
The PMOS(Q2) gate drive is exactly twice this value.
R4 - This resistors pulls the base of Q1 up to Vbatt.
Coupled with Q1 and C7 it is part of the 5V regulator
that supplies the working power to the AME9003. When
the PNP pin is turned off the base of Q1 is pulled high
through R4, turning off Q1 and allowing the voltage at
the VDD node (VSUPPLY) to decay towards zero.
Q1 - This common PNP transistor (2n3906 is adequate)
forms part of the 5V linear regulator which supplies
power to most of the AME9003.
R6 - This resistor, together with adjustable resistor
R20, form a resistor divider that divides the regulated
5V down to some lower voltage. That lower voltage is
used to drive the BRIGHT pin which, in turn, deter-
mines the duty cycle of the the dimming cycles and
therefore the brightness of the lamps. If the user is
driving the BRIGHT pin with his/her own voltage source
then R6 and R20 are not necessary.
C6 - This capacitor bypasses the BRIGHT pin. A noisy
BRIGHT pin can cause unwanted flicker.
R20 - see description of R6
C14 - Note that the 9003 has a ” soft finish” as well as
a ” soft start” feature. This capacitor sets the slope of
the soft-start (soft-finish) ramp on pin SSV. The volt-
age at SSV limits the duty cycle of the Q2 gate drive
signal available at pin OUTA. The voltage at the COMP
node is internally clamped to the SSV node. There-
fore the C14 cap limits how fast SSV, and hence, COMP
can increase (and decrease). Limiting COMP in-
crease (decrease) will limit the rate of increase (or de-
crease) of the switching duty cycle thereby creating a
” soft start (soft finish)” effect. The charging/discharging
current out of SSV is approximately 10uA so the rate
of change of the SSV voltage is:
SSV(Volts/sec) = (10e-6amps) / C14