AME9003 Datasheet, PDF (2/39 Pages) Asahi Kasei Microsystems – CCFL Backlight Controller

AME, Inc.
AME9003
n Pin Description
Preliminary
CCFL Backlight Controller
Pin #
1
2
3
4
5
6
7
8
9
10
Pin Name
VREF
CE
SSC
RDELTA
SSC1ST
RT2
VSS
OVPH
OVPL
FCOMP
Pin Description
Reference. Compensation point for the 3.4V internal voltage reference. Must have
bypass capacitor connected here to VSS.
Chip enable. When low (<0.4V) the chip is put into a low current (~0uA) shutdown
mode.
Blanking interval ramp. During the first cycle this pin sources 1.5uA. The first cycle is
used to define the initial start up period, often on the order of one second. During
subsequent cycles SSC sources 140mA. This is primarily used to provide a "blanking
interval" at the beginning of every dimming cycle to temporarily disable the fault
protection circuitry. The blanking interval is active when V(SSC) < 3.0 volts. (See
application notes.)
A resistor connected from this pin to VDD determines the amount that the voltage at
FCOMP modulates the switching frequency. The frequency is inversely proportional to
the voltage at FCOMP.
A capacitor added between this pin and SSC is used to define the one second initial
start up period. SSC1ST is connected to VSS for the start up period and floats for
subsequent periods.
A resistor from this pin to VSS sets the minimum frequency of the VCO. The voltage at
this pin is 1.5V
Negative supply. Connect to system ground.
Over voltage protection input (HIGH). Indirectly senses the voltage at the secondary of
the transformer through a resistor (or capacitor) divider. During the initial start up
period, if OVPH is > 3.3V, FCOMP is driven towards VSS (increasing the frequency)
and SSV is reset to zero (which decreases the duty cycle). After the initial start up
period is completed the circuit will shut down if OVPH is > 3.3V.
Over voltage protection input (LOW). During the initial start up period if OVPL < 2.5
volts then FCOMP is allowed to ramp up (decreasing the oscillator frequency allowing
the circuit to get closer to resonance). If, during the initial start up period, OVPL > 2.5
volts then FCOMP is held at its original value (not allowed to increase so the
oscillator frequency stays constant). This action is designed to hold the voltage
across the CCFL constant while the CCFL "warms up".
Frequency control point. Initially this pin is at VSS which yields a maximum switching
frequency. Depending on the voltage at OVPL and OVPH the pin FCOMP will normally
ramp upwards lowering the switching frequency towards the circuit's resonant
frequency.
2