AME9003 Datasheet, PDF (19/39 Pages) Asahi Kasei Microsystems – CCFL Backlight Controller

AME, Inc.
AME9003
Preliminary
CCFL Backlight Controller
These conditions allow the voltage across the CCFL to
be controlled during the start up period. The two thresh-
olds available at OVPL and OVPH allow the user to tailor
the start behavior for particular tubes.
In Figure 11, initially SSV=SSC=FCOMP= zero volts.
The switching duty cycle is zero, the switching frequency
is maximum and the one second time period ramp has
just started. The SSV ramps positive which allows the
switching duty cycle to increase which, in turn, increases
the voltage across the CCFL.
At some point later SSV=5 volts, SSC and FCOMP
are still ramping up. The tube voltage continues to in-
crease, the switching duty cycle is no longer limited by
SSV and is able to go to 100%, if indicated by the error
amp loop. The switching frequency continues to decrease
forcing the tube voltage higher. If the CCFL voltage is
high enough so that OVPL > 2.5V (OVPL senses the
CCFL voltage through a resistor or capacitor divider) then
FCOMP stops increasing and the frequency remains con-
stant. The frequency will remain constant until:
OVPL < 2.5V
OR....
OVPH > 3.3V (see below)
OR......
The one second time period runs out and the
circuit shuts down.
If the voltage across the tube increases enough so that
OVPH > 3.3V (as sensed through a resistor or capacitor
divider) then FCOMP is pulled low (~1V), the switching
frequency is increased, SSV is pulled low and the switch-
ing duty cycle goes to zero. It will remain in this state
until:
OVPH < 3.3V
OR....
The one second time period runs out and the circuit
shuts down.
Ideally, during one of these states, the CCFL will strike,
current will flow in the CCFL and the circuit will move
from the start up mode into the steady state mode. Once
an arc has struck, as sensed by CSDET > 1.25 volts,
then the circuit will drive the CCFL at 100% brightness
for approximately two dimming cycles (dimming cycles
are on the order of 6mS as determined by the capacitor
on CT1) in order to ensure that the CCFL is really ” on” .
After those two full brightness dimming cycles the nor-
mal duty brightness control takes over, alternately turn-
ing the CCFL on and off at a duty cycle determined by
the voltage at the BRIGHT pin.
Remember, the circuit will only ” try” to turn on for one
second, after that point it gives up and shuts down.
Steady State Mode
At the beginning of each dimming cycle (after the start
up mode) there is initially no arc struck in the CCFL. The
CCFL load looks like an open circuit. (However an arc
has been struck successfully in the start up mode so we
assume the gas has ” warmed up” and is ready to strike
an arc again.) SSV is pulled to zero volts then ramps to 5
volts allowing the duty cycle of the switches to slowly
increase to its steady state value. The voltage across
the CCFL will increase with each successive clock cycle.
Two events may then happen:
1) The gas inside the CCFL will ionize, the voltage across
the CCFL will drop, the current through the CCFL will
increase, and a stable steady state operating point
will be reached.
OR....
2) One of the three fault conditions will be met that shut
down the circuit (see Figure 11):
a) The CCFL tube voltage continues to rise until the
OVPH pin is higher than 3.3V at which point the
circuit will shut down (immediately).
b) The CCFL tube voltage continues to rise until the
OVPL pin is higher than 2.5V at which point the
circuit will shut down (except during the blanking
interval).
c) The CCFL current fails to rise high enough to keep
the undercurrent threshold at the CSDET pin from
tripping (for 8 consecutive clock cycles).
Note that condition a) can be met at any time while the
AME9003 is in steady state operation (after the start up
mode). Condition b) can only be met after the SSC pin
has risen above 3V (after blanking interval). Condition c)
can only be met after the SSC pin has crossed 3V (after
blanking interval) AND eight successive undercurrent
events occur in a row (CSDET < 1.25V for 8 consecutive
clock cycles.).
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