AME9003 Datasheet, PDF (20/39 Pages) Asahi Kasei Microsystems – CCFL Backlight Controller

AME, Inc.
AME9003
Preliminary
CCFL Backlight Controller
The SSC pin is pulled to VSS everytime the lamp is
turned off, whether for a dimming cycle, user shutdown
or fault occurrence. It ramps up slowly depending on the
size of capacitor C3 connected to the SSC pin (in steady
state mode SSC1ST is high impedance so capacitor C31
has no effect). The period of time when the b) and c) fault
checks are disabled is called the lanking? time. The
blanking time occurs from the time SSC is pulled to VSS
until it reaches 3V. See Figure 9 for some idealized wave-
forms illustrating the behavior just described.
Control Algorithm
There are 2 major control blocks (loops) within the IC.
The first loop controls the duty cycle of the driving wave-
form. It senses the CCFL current (Figure 1 or 2, resistor
R9 and R10) rectifies it, integrates it against an internal
reference and adjusts the duty cycle to obtain the de-
sired power. This loop uses error amplifier EA1 whose
negative input is pin FB and whose output is COMP. The
positive input of EA1 is connected to a 2.5V reference.
External components, R7 and C8, set the time constant
of the integrator, EA1. In order to slow the response of
the integrator increase the value of the product:
(R7 X C8).
The second control block adjusts the brightness by
turning the lamp on and off at varying duty cycles. Each
time the lamp turns on and off is referred to as a ” dim-
ming cycle” . At the end of each dimming cycle the SSV
pin is pulled low with a 10uA current source, this forces
COMP low as well due to the clamping action of Clamp1
shown in Figure 1. At the beginning of a new dimming
cycle COMP tries to increase quickly but it is clamped to
the voltage at the SSV(soft-start voltage) pin. A capacitor
on the SSV pin (C8, Figure 1), which is discharged at the
end of every dimming cycle, sets the slew rate of the
positive and negative edge of the voltage at the SSV pin,
and hence also the maximum positive (and negative) slew
rate of the COMP pin. ” Dimming cycle” is explained
more fully below]
The BRIGHT, CT1 and BRPOL pins
A user-provided voltage at the BRIGHT pin is compared
with the ramp voltage at the CT1 pin (See Figure 12). If
BRPOL is tied to VSS then as the voltage at BRIGHT
increases the duty cycle of the dimming cycle and the
brightness of the CCFL increase. If BRPOL is tied to
VDD then the brightness of the CCFL diminishes as the
BRIGHT voltage increases. The frequency of the dim-
ming cycles is set by the value of the capacitor at pin
CT1 (C4 in Figure 1 and 2) and it is also proportional to
the current set by resistor R2. Setting C4 equal to
0.047uF and R2 equal to 47.5k yields a dimming cycle
frequency of approximately 125Hz. The frequency should
vary inversely with the value of C4 according to the rela-
tion:
Frequency(Hz) = 1/[4 X R2 X C4]
The brightness may also be controlled by using a vari-
able resistor in place of R10 (See Figure 13). In this case
the BRIGHT pin should be pulled to VDD so that the CCFL
remains on constantly. This method can lead to flicker at
low intensities but it is easy to implement. Harmonic
distortion may also increase since the duty cycle of the
waveform at the gate of Q2 will vary greatly with bright-
ness. When using burst brightness control the duty cycle
of the driving waveforms should not vary because the
CCFL is running at 100% power or it is turned off. As
long as the battery voltage does not change the duty cycle
of the driving waveform also does not change greatly. This
means that harmonic distortion can be minimized by op-
timizing the frequency and transformer characteristics for
a particular duty cycle rather than a large range of duty
cycle.
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