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AK2572 Datasheet, PDF (26/50 Pages) Asahi Kasei Microsystems – APC for Burst Mode Applicable Direct Modulation Laser Diode | |||
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ASAHI KASEI
[AK2572]
Table 5-1 EEPROM Address Space in Power Leveling [1]
RE_MODV_SEL
1
0
MOD_CTRL-pin
H
L
H
L
EEPROM Device Address Address
DAC
E_MOD_TC [2]
A0h
00h ~ 7Dh [*] V-DAC3
ï¼
I-DAC1
ï¼
E_MOD_TC [1]
A4h
00h ~ 7Fh
ï¼
V-DAC3
ï¼
I-DAC1
E_BIAS_TC
A4h
80h ~ FFh
I-DAC2
I-DAC2
I-DAC2
I-DAC2
E_EXTRA_TC
A6h
00h ~ 1Fh
I-DAC1
I-DAC1 V-DAC3 V-DAC3
[*] Since Write Protect control register is allocated at âDevice Addressï¼A0h / Addressï¼7Eh, 7Fhâ, E_MOD_TC
[2] has 126 address locations. Therefore E_MOD_TC [2] has 2 fewer address locations as compared with
E_MOD_TC [1] and E_BIAS_TC. So the linear interpolation of E_MOD_TC [2] is executed as follows :
R_MOD_FF(z)ï¼E_MOD_TC2(xï¼1)ï¼ï½E_MOD_TC2(x)ï¼E_MOD_TC2(xï¼1)ï½ÃR_TEMP [0] / 2
when zï¼R_TEMP [7:0]ï¼0 ~ 5, E_MOD_TC(x)ï¼E_MOD_TC(xï¼1)ï¼E_MOD_TC(0)
where the detected temperature data is R_TEMP [7:0]ï¼zï¼2x+5,2x+4, R_TEMP [7:1]ï¼x, E_MOD_TC[2] as
E_MOD_TC2(x) and the obtained data by a linear interpolation is R_MOD_FF(z).
5. 2 Power Leveling [2]
In Power Leveling [2] mode, the data to be loaded to register (R_BIAS_FF, R_MOD_FF) can be selected by
R_PWR_SEL setting among 4 patterns of Bias current and Modulation current temperature compensation
data that are retained in EEPROM.
Power Leveling [2] is enabled by setting RE_PWR_LVL1_SETï¼â0â and RE_PWR_LVL2_SETï¼â1â.
When the write protect is released (WP-pinï¼âHâ and R_WP_CTRLï¼â0â), R_PWR_SEL [1:0] data at âDevice
Addressï¼A8h / Addressï¼2Fhâ can be altered in Self-Operation Mode.
When Power Leveling [2] is enabled, a linear interpolation of the temperature compensation data is executed by
using R_TEMP [7:3], R_TEMP [2:0] and the data in EEPROM as shown in Table 5-2.
R_BIAS_FF(z)ï¼E_BIAS_TCn(yï¼1)ï¼ï½E_BIAS_TC n(y)ï¼E_BIAS_TCn(yï¼1)ï½ÃR_TEMP [2:0] / 8
R_MOD_FF(z)ï¼E_MOD_TCn(yï¼1)ï¼{E_MOD_TCn(y)ï¼E_MOD_TCn(yï¼1)}ÃR_TEMP [2:0] / 8
when yï¼0 (R_TEMP [7:0]ï¼zï¼0~7), E_BIAS_TCn(y)ï¼E_BIAS_TCn(yï¼1)ï¼E_BIAS_TCn(0) and
E_MOD_TCn(y)ï¼E_MOD_TCn(yï¼1)ï¼E_MOD_TCn(0).
where the detected temperature data R_TEMP [7:0]ï¼zï¼8y, 8y+1, ã»ã»ã», 8y+7, R_TEMP [7:3]ï¼y, the
temperature compensation data retained in EEPROM is E_BIAS_TCn(y), E_MOD_TCn(y), nï¼0~3 and the
obtained data by a linear interpolation is R_BIAS_FF(z), R_MOD_FF(z) respectively.
Table 5-2 EEPROM Address Space in Power Leveling [2]
RE_ PWR_LVL2_SETï¼â0â
RE_ PWR_LVL2_SETï¼â1â
R_TEMP ï¼»7:1ï¼½ Data
Address RE_PWR_SEL R_TEMP ï¼»7:3ï¼½ Data
Address
0
00h ~ 1Fh E_MOD0_TC 00h ~ 1Fh
00h ~ 7Fh E_MOD_TC 00h ~ 7Fh
1
00h ~ 1Fh E_MOD1_TC 20h ~ 3Fh
2
00h ~ 1Fh E_MOD2_TC 40h ~ 5Fh
3
00h ~ 1Fh E_MOD3_TC 60h ~ 7Fh
0
00h ~ 1Fh E_BIAS0_TC 80h ~ 9Fh
00h ~ 7Fh E_BIAS_TC 80h ~ FFh
1
00h ~ 1Fh E_BIAS1_TC A0h ~ BFh
2
00h ~ 1Fh E_BIAS2_TC C0h ~ DFh
3
00h ~ 1Fh E_BIAS3_TC E0h ~ FFh
-26-
< MS0290-E-01>
2004/8
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