AK4641 Datasheet, PDF (25/51 Pages) Asahi Kasei Microsystems – 16 BIT CODEC WITH BLUETOOTH INTERFACE

ASAHI KASEI
[AK4641]
[3] Example of ALC1 Operation
Table 11 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB.
Register Name
LMTH
LTM1-0
ZELM
ZTM1-0
WTM1-0
REF6-0
IPGA6-0
LMAT1-0
RATT
ALC1
Comment
fs=8kHz
fs=16kHz
Data Operation Data Operation
Limiter detection Level
1 −4dBFS 1 −4dBFS
Limiter operation period at ZELM = 1 00 Don’t use 00 Don’t use
Limiter zero crossing detection
0 Enable 0 Enable
Zero crossing timeout period
00
16ms
01
16ms
Recovery waiting period
*WTM1-0 bits should be the same data 00
16ms
01
16ms
as ZTM1-0 bits
Maximum gain at recovery operation 47H +27.5dB 47H +27.5dB
Gain of IPGA at ALC1 operation Start 10H 0dB 10H 0dB
Limiter ATT Step
00 1 step 00 1 step
Recovery GAIN Step
0
1 step
0
1 step
ALC1 Enable bit
1 Enable 1 Enable
Table 11. Example of the ALC1 setting
fs=44.1kHz
Data Operation
1 −4dBFS
00 Don’t use
0 Enable
10 11.6ms
10 11.6ms
47H +27.5dB
10H 0dB
00 1 step
0
1 step
1 Enable
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1
operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.
• LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is “1” and
ALC1 bit is “0”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
Manual Mode
WR (ZTM1-0, WTM1-0, LTM1-0)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level = −4dBFS
(1) Addr=08H, Data=00H
WR (REF6-0)
(2) Addr=0AH, Data=47H
WR (IPGA6-0) ^{* The value of IPGA should be}
the same or smaller than REF’s
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
(3) Addr=0BH, Data=10H
(4) Addr=09H, Data=21H
ALC1 Operation
* ALC1 bit must be set to “1” at more than zero cross time out period
after the value of IPGA is set (see figure 22).
Note : WR : Write
Figure 23. Registers set-up sequence at ALC1 operation
MS0301-E-00
- 25 -
2004/05