AK4641 Datasheet, PDF (16/51 Pages) Asahi Kasei Microsystems – 16 BIT CODEC WITH BLUETOOTH INTERFACE

ASAHI KASEI
[AK4641]
OPERATION OVERVIEW
„ System Clock Input
The AK4641 requires a master clock (MCLK). This master clock is input to the AK4641 by inputting an external
CMOS-level clock to the MCLK pin or by inputting an external clock that is greater than 50% of the DVDD level to the
MCLK pin through a capacitor. MCKPD and MCKAC bits should be set as shown in Table 1. ADC and DAC of 16bit
Stereo CODEC are powered-down at MCKPD bit = “1”.
Master Clock
Status
MCKAC bit
External Clock Direct Input (Figure 12) Clock is input to MCLK pin.
0
Clock is not input to MCLK pin.
0
AC Coupling Input
(Figure 13) Clock is input to MCLK pin.
1
Clock is not input to MCLK pin.
1
Table 1. MCKPD and MCKAC bits Setting for Master Clock Status
MCKPD bit
0
1
0
1
(1) External Clock Direct Input
MCLK
External
Clock
MCKAC bit = "0"
MCKPD bit = "0"
AK4641
Figure 12. External Master Clock Input Block
(2) AC Coupling Input
0.1uF _MCLK
External
Clock
MCKAC bit = "1"
MCKPD bit = "0"
AK4641
Figure 13. External Clock mode (Input: ≥ 50%DVDD)
MS0301-E-00
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2004/05