AK4641 Datasheet, PDF (17/51 Pages) Asahi Kasei Microsystems – 16 BIT CODEC WITH BLUETOOTH INTERFACE

ASAHI KASEI
[AK4641]
The clock required to operate are MCLK, LRCK (fs) and BICK (≥ 32fs). Then the master clock (MCLK) should be
synchronized with LRCK. The phase between these clocks does not matter.
The S/N of the DAC of Stereo CODEC at low sampling frequencies is worse than at high sampling frequencies due to
out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the
DAC output of Stereo CODEC through Headphone amp at fs=8kHz is shown in Table 3.
MCK1
0
0
1
1
MCK0
0
1
0
1
Sampling Frequency
MCLK
(fs)
7kHz∼48kHz
256fs
7kHz∼24kHz
512fs
7kHz∼12kHz
1024fs
-
N/A
Table 2. Select Master Clock Frequency
Default
MCLK S/N (fs=8kHz, A-weighted)
256fs
82dB
512fs
90dB
1024fs
90dB
Table 3. Relationship between MCLK and S/N of Line Out
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4641 may
occur pop noise.
All external clocks (MCLK, BICK and LRCK) should always be present when either ADC or DAC of Stereo CODEC is
power-up. If these clocks are not provided, the AK4641 may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4641 should be in the
power-down mode.
BICK pin
LRCK pin
Power up
Power down
Input
Fixed to “L” or “H” externally
Input
Fixed to “L” or “H” externally
Table 4. Clock Operation
„ System Reset
Upon power-up, reset the AK4641 by bringing the PDN pin = “L”. This ensures that all internal registers are reset to their
initial values.
The ADC of Stereo CODEC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The
initialization cycle time is 2081/fs, or 47.2ms@fs=44.1kHz. During the initialization cycle, the ADC digital data output of
Stereo CODEC is forced to a 2's compliment, “0”. The ADC output of Stereo CODEC reflects the analog input signal
after the initialization cycle is complete. The DAC of Stereo CODEC does not require an initialization cycle.
The ADC of Mono CODEC enters an initialization cycle that starts when the PMAD2 bit is changed from “0” to “1”. The
initialization cycle time is 1057/Bfs, or 132ms@Bfs=8kHz. During the initialization cycle, the ADC digital data output of
Mono CODEC is forced to a 2's compliment, “0”. The ADC output of Mono CODEC reflects the analog input signal after
the initialization cycle is complete. The DAC of Mono CODEC does not require an initialization cycle.
MS0301-E-00
- 17 -
2004/05