AK4589 Datasheet, PDF (22/76 Pages) Asahi Kasei Microsystems – 2/8 CHANNEL AUDIO CODEC WITH DIR

ASAHI KASEI
[AK4589]
εΠονϯάಛੑ ADC/DAC෦, DIR/DIT෦
ڞ௨

(Ta=25°C; AVDD, DVDD, PVDD=4.75∼5.25V; TVDD=2.7∼5.25V; C_L=20pF)
Parameter
Symbol
min
typ
Control Interface Timing (4-wire serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I²C Bus mode)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 23)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
tCCK
200
tCCKL
80
tCCKH
80
tCDS
50
tCDH
50
tCSW
150
tCSS
50
tCSH
50
tDCD
tCCZ
fSCL
-
tBUF
4.7
tHD:STA 4.0
tLOW
4.7
tHIGH
4.0
tSU:STA
4.7
tHD:DAT
0
tSU:DAT 0.25
tR
-
tF
-
tSU:STO
4.0
tSP
0
Cb
-
Notes:
23. σʔλ͸࠷௿300ns (SCLͷཱͪԼ͕Γ࣌ؒ) ͷؒอ࣋͞Εͳ͚Ε͹ͳΓ·ͤΜɻ
24. I²C͸Philips Semiconductorsͷొ࿥঎ඪͰ͢ɻ
max Units
ns
ns
ns
ns
ns
ns
ns
ns
45
ns
70
ns
100 kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
1.0
µs
0.3
µs
-
µs
50
ns
400
pF
ѴԽ੒ϚΠΫϩγεςϜʢגʣ੡I²CόεɾίϯϙʔωϯτΛߪೖͨ͠৔߹ɺPhilipsͷ࣋ͭI²Cಛݖڐͷ
ԼɺI²CόεɾγεςϜ಺Ͱ͜ΕΒͷίϯϙʔωϯτΛ࢖༻͢ΔͨΊͷϥΠηϯε͕༩͑ΒΕ·͢ɻͨ
ͩͦ͠ͷόεɾγεςϜ͕ɺPhilipsͷنఆ͢ΔI²C࢓༷ʹ४͍ͯ͠ڌΔ৔߹ʹݶΓ·͢ɻ
MS0339-J-00
- 22 -
2004/09