AK4220 Datasheet, PDF (22/33 Pages) Asahi Kasei Microsystems – 7:3 Audio Switch and 6:3 Video Switch

I
[AK4220]
■ Serial Control Interface
1. 4 wire serial control mode (IICN pin = “H”)
With the 4-wire μP interface pins (CSN, CCLK, CDTI and CDTO), the data on this interface consists of the Chip address
(2-bits, Fixed to “00”), Read/Write (1-bit), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). The
data are clocked in on the rising edge of CCLK, and data are clocked out on the falling edge of CCLK. For write
operations, the data is latched after a low-to-high transition of the 16th CCLK. For read operation, the data is outputted to
Hi-Z on the rising edge of CSN. The clock speed of CCLK is 5MHz(max). The value of the internal registers is initialized
at PDN pin = “L”.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
WRITE
CDTO
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
READ
CDTI
CDTO
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0
C1,C0:
R/W:
A4-A0:
D7-D0:
Chip Address: ( Fixed to “00”)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 19. 4-wrie Serial Control I/F Timing
MS0627-E-00
- 22 -
2007/05