AK4220 Datasheet, PDF (19/33 Pages) Asahi Kasei Microsystems – 7:3 Audio Switch and 6:3 Video Switch

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[AK4220]
2. VDET bit (Video Sync Signal Detection)
The video sync signal detection circuit can change the detection mode by VDMD bit.
VDMD bit =“0” (default)
When video sync signal above 0.07Vpp(typ) is detected, VDET bit become “1” and VDET bit returns to “0” after reading
the register of 08H. The VDET bit is also reset to “0” by writing to the register of 04H with VDSEL2-0 bits.
When writing to 04H(VDSEL2-0 bits) the VDET bit become “0”.
VDMD bit =“1”
The detection circuit counts the number of video sync signal above 0.07Vpp(typ) every 40ms(±30%) period generated by
the internal counter. When the period with the sync of 384 or more continues tow times, the VDET bit becomes “1” after
1/2 period. When the period with the sync signal less than 384 continues tow times, the VDET bit becomes “0” after 1/2
period.
The internal timer isn’t reset when changing the input source. Therefore the detection time, from after changing the input
source to VDET bit = “1”, depends on the timing of input source change.
In case of a period that the internal timer count is the shortest(40ms x 70% = 28ms), when the detection circuit counts 384
times during the first period that receives video sync signal and counts 384 times or more in the following period, the
detection time becomes the shortest.
Detection time (min) = (1/fH) x 384 + 28ms x 1.5 ≅ 66.6ms @ fH=15.625kHz
fH: frequency of video synchronization signal
If a period that internal timer counts is the longest (40ms x 130% = 52ms), when the detection circuit counts only 383
times during the first period that receives video sync signal and counts 384 times or more in the following two periods, the
detection time becomes the longest.
Detection time (max) = (1/fH) x 384 + 52ms x 2.5 ≅ 154.5ms @ fH=15.625kHz
fH: frequency of video synchronization signal
When writing to 04H(VDSEL2-0bits), the internal timer is reset and VDET bit becomes “0”.
The setting of MVDET bit doesn’t affect the operation of VDET bit.
Input pin
(ex. VIN1)
VDET bit
Input pin
(ex. VIN1)
VDET bit
1st period
2nd period
3rd period
4th period
≥384 times
≥384 times
“0”
“1”
≤384 times
≥384 times
≥384 times
“0”
“1”
Figure 15. VDET bit timing (VDMD bit =“1”)
MS0627-E-00
- 19 -
2007/05