AK4220 Datasheet, PDF (14/33 Pages) Asahi Kasei Microsystems – 7:3 Audio Switch and 6:3 Video Switch

I
[AK4220]
OPERATION OVERVIEW
■ Power-down options
The AK4220 should be reset once by bringing PDN pin = “L” upon power-up.
■ Audio Bias Control Circuit
The AK4220 has an on-chip audio bias voltage control circuit. Bringing BIAS bit to “1”, the bias voltage (MUTET pin)
smoothly set from AVSS to AVDD/2(typ) by 150ms (typ, Note: 23). The change of BIAS bit from “1” to “0” also makes
smooth transient from AVDD/2(typ) to AVSS by 150ms (typ, Note: 23). This feature achieves pop noise free at
power-on/off.
Note: 23. AVDD=5.0V, the capacitor of MUTET pin is C=1uF. The rise and fall times are proportional to the voltage of
AVDD and the capacitor value of MUTET pin.
PDN pin
BIAS bit
“0” (default)
“1”
Audio bias level
150ms (typ)
“0”
150ms (typ)
Figure 13. BIAS bit
■ Audio Signal Input, Video Signal Input
1. Audio Signal Input
The ground noise can be cancelled by the differential input with the same ground for L and R channel. The output of LIN
and RIN are the same phase. LIN+1-7, RIN+1-7 and GND1-7 pins must be AC coupled using 0.47uF capacitor.
2. Video Signal Input
Tip Sync level is fixed by internal clamp circuit. VIN1-6 pins must be input through 0.47uF capacitor for AC coupling.
MS0627-E-00
- 14 -
2007/05