AK5367 Datasheet, PDF (21/28 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ΔΣ ADC with 0V Bias Selector

[AK5367]
■ Serial Control Interface
The AK5367 supports the first-mode I²C-bus system (max: 400kHz).
The pull-up resistance of SDA,SCL pins should be connected below the voltage of DVDD+0.3V.
1. WRITE Operations
Figure 15 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 21). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant 7 bits of the slave address are fixed as “0110001”. If the slave address matches that of the
AK5367, the AK5367 generates an acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 22). A
R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK5367. The format is MSB first, and those most
significant 6-bits are fixed to zeros (Figure 17). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 18). The AK5367 generates an acknowledge after each byte is received. A data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 21).
The AK5367 can perform more than one byte write operation per sequence. The master can transmit more than one byte
instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal
2-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 02H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will
be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 23) except for the START and STOP
conditions.
S
T
S
A
R/W="0"
T
R
O
T
P
SDA
Slave
S _Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 15. Data Transfer Sequence at the I²C-Bus Mode
0
1
1
0
0
0
1
R/W
Figure 16. The First Byte
0
0
0
0
0
0
A1
A0
Figure 17. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 18. Byte Structure after the second byte
MS0694-E-00
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2007/12