AK5367 Datasheet, PDF (17/28 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ΔΣ ADC with 0V Bias Selector

[AK5367]
■ System Reset
The AK5367 should be reset once by bringing PDN pin “L” after power-up. At the slave mode, the internal timing starts
clocking by the rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.
The AK5367 is in power-down states until the LRCK is input. At the master mode, bringing PDN pin “H” and exiting
from reset and power down state by MCLK input.
■ Soft Mute Operation
Soft mute operation is performed in the digital domain of the ADC output. When SMUTE bit goes “1”, the ADC output
data is attenuated to −∞ within 1024 LRCK cycles. When the SMUTE bit returned “0”, the mute is cancelled and the
output attenuation gradually changes to 0dB within 1024 LRCK cycles. If the soft mute is cancelled before mute state
after starting of the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing
the signal source without stopping the signal transmission.
SMUTE bit
0dB
A tte n u a tio n
-∞
1024/fs
(1)
1024/fs
(2)
SDTO Output Data
“0” data
Figure 11. Soft Mute Function
Notes:
(1) The output signal is attenuated by −∞ within 1024 LRCK cycles (1024/fs).
(2) If the soft mute is cancelled before the mute, the attenuation is discontinued and returned to 0dB by the same cycle.
■ Input Selector
The AK5367 includes 4ch stereo input selectors. The input selector is 4 to 1 selector and set by SEL2-0 bits (Table 4).
SEL2 bit
0
0
0
0
1
SEL1 bit
0
0
1
1
0
Note: The LOUT, ROUT pin are 0V.
SEL0 bit
Input Selector
0
LIN1 / RIN1
1
LIN2 / RIN2
0
LIN3 / RIN3
1
LIN4 / RIN4
0
All off (Note)
Table 4. Input Selector
(default)
MS0694-E-00
- 17 -
2007/12