AK5367 Datasheet, PDF (15/28 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ΔΣ ADC with 0V Bias Selector

[AK5367]
■ Audio Interface Format
Two kinds of data formats can be chosen with the DIF bit (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of BICK. The audio interface supports both master and
slave modes. In master mode, BICK and LRCK are output with the BICK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF bit
0
1
SDTO
LRCK BICK(Slave) BICK(Master)
24bit, MSB justified H/L ≥ 48fs or 32fs
64fs
24bit, I²S Compatible L/H ≥ 48fs or 32fs
64fs
Table 3. Audio Interface Format
Figure
Figure 8
Figure 9
(default)
LRCK
012
BICK(64fs)
20 21 22 23 24
31 0 1 2
SDTO(o)
23 22
43210
23 22
23:MSB, 0:LSB
Lch Data
Figure 8. Mode 0 Timing
20 21 22 23 24
43210
Rch Data
31 0 1
23
LRCK
0123
BICK(64fs)
21 22 23 24 25
012
21 22 23 24 25
01
SDTO(o)
23 22
43210
23 22
23:MSB, 0:LSB
Lch Data
Figure 9. Mode 1 Timing
43210
Rch Data
■ Master Mode and Slave Mode
The AK5367 becomes slave mode when it is in the power-down mode (PDN pin = “L”) or exiting power-down. After
exiting the power-down mode, master mode should be set by CKS0-2 bits.
In master mode, LRCK and BICK pins are floating until CKS0-2 bits fixed. Therefore BICK and LRCK pins must be
connected with 100 kΩ pull-up or pull-down resistance.
MS0694-E-00
- 15 -
2007/12