AK5367 Datasheet, PDF (10/28 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ΔΣ ADC with 0V Bias Selector

SWITCHING CHARACTERISTICS
(Ta=-20°C ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
512fs, 256fs Frequency
fCLK
8.192
Pulse Width Low
tCLKL
16
Pulse Width High
tCLKH
16
768fs, 384fs Frequency
fCLK
12.288
Pulse Width Low
tCLKL
10.5
Pulse Width High
tCLKH
10.5
LRCK Frequency
fs
32
Duty Cycle
Slave mode
45
Master mode
50
Audio Interface Timing
Slave mode
BICK Period
tSCK
160
BICK Pulse Width Low
tSCKL
65
Pulse Width High
tSCKH
65
LRCK Edge to BICK “↑”
(Note 14) tLRSH
30
BICK “↑” to LRCK Edge
(Note 14) tSHLR
30
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
BICK “↓” to SDTO
tSSD
Master mode
BICK Frequency
fSCK
64fs
BICK Duty
dSCK
50
BICK “↓” to LRCK
tMSLR
−20
BICK “↓” to SDTO
tSSD
−20
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
fSCL
-
tBUF
1.3
tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 15) _tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise
tSP
0
Suppressed by Input Filter
Capacitive load on bus
Cb
-
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. Data must be held long enough to bridge the 300ns-transition time of SCL.
[AK5367]
max
24.576
36.864
96
55
Units
MHz
ns
ns
MHz
ns
ns
kHz
%
%
ns
ns
ns
ns
ns
35
ns
35
ns
Hz
%
20
ns
35
ns
400
kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
0.3
μs
0.3
μs
-
μs
50
ns
400
pF
MS0694-E-00
- 10 -
2007/12