AK5720 Datasheet, PDF (18/25 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ADC

[AK5720]
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=48kHz) and scales with sampling rate (fs).
■ Power Down
The AK5720 is placed in the power-down mode by bringing the PDN pin to “L”. The digital filter is also reset
at the same time. This reset should always be executed upon power-up. In power-down mode, VCOM
becomes VSS level. The AK5720 will be in analog initialization cycle after exiting the power-down mode.
Therefore, the SDTO output data becomes valid after 4129 cycles of LRCK clock in master mode or 4132
cycles of LRCK clock in slave mode when power up the AK5720. During initialization, both L and R channels
of ADC digital data outputs are forced to “0” in 2’s complement. The ADC outputs settle as a data
corresponding to the input signals after the end of initialization (this settling takes approximately group delay
time).
VA/VD
PDN
(1)
VCOM
REGO
Internal PDN
ADC Internal
State
(2)
(3)
3~4/fs
4129/fs ⁽⁴⁾
Init Cycle
ADC In
(Analog)
ADC Out
“0”data
(5)
(Digital)
Normal Operation
Power-down
GD ⁽⁶⁾
GD
(7) “0”data
Clock In
Don’t care
MCLK,LRCK,BICK
Don’t care
Figure 12. Power-down/up Timing Example
Notes:
(1) The PDN pin must be “L” when power up the AK5720 and set to “H” after all poweres are supplied.
(2) The internal power-down state is released after 147456/ MCLK cycles.
(3) There is a delay about 3~4fs from internal power-up to the start of initialization cycle.
(4) Digital block of the ADC is initialized after internal power-down is released.
When start-up the AK5720, ADC input voltage should be operation common voltage.
A charge-up time of DC cut capacitor is necessary to wait until the RIN and LIN pins settle to the
common voltage. When the external capacitor is 10µF, the status of these pin settles in τ= 400ms (typ).
(5) Click noise occurs at the end of initialization in the digital part. Mute the ADC output externally if the
click noise influences system applications.
(6) Digital output corresponds to analog input has group delay (GD).
(7) ADC outputs “0” data in power-down state.
MS1641-E-02
- 18 -
2014/12