AK5720 Datasheet, PDF (11/25 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ADC

[AK5720]
Parameter
Symbol min
typ
max
Unit
Audio Interface Timing (Slave mode)
Normal mode
BICK Period
tBCK
160
BICK Pulse Width Low
tBCKL
65
Pulse Width High
LRCK Edge to BICK “”
(Note 8) ^tBCKH
65
tLRB
30
BICK “” to LRCK Edge (Note 8)
LRCK to SDTO (MSB) (Except I²S
tBLR
tLRS
30
mode)
tBSD
BICK “” to SDTO
ns
ns
ns
ns
ns
35
ns
35
ns
TDM256 mode
BICK Period
tBCK
40
ns
BICK Pulse Width Low
tBCKL
16
ns
Pulse Width High
tBCKH
16
ns
LRCK Edge to BICK “”
(Note 8) tLRB
10
ns
BICK “” to LRCK Edge
(Note 8) tBLR
10
ns
SDTO Setup time BICK “”
tBSS
7
ns
SDTO Hold BICK “”
tBSH
6
ns
TDMI Hold Time
tSDH
4
ns
TDMI Setup Time
tSDS
5
ns
Audio Interface Timing (Master mode)
Normal mode
BICK Frequency
fBCK
64fs
Hz
BICK Duty
dBCK
50
%
BICK “” to LRCK
tMBLR
20
20
ns
BICK “” to SDTO
tBSD
40
40
ns
TDM256 mode
BICK Frequency
fBCK
256fs
Hz
BICK Duty
(Note 9) dBCK
50
%
BICK “” to LRCK
tMBLR
10
10
ns
SDTO Setup time BICK “”
tBSS
7
ns
SDTO Hold BICK “”
tBSH
6
ns
TDMI Hold Time
tSDH
4
ns
TDMI Setup Time
tSDS
5
ns
Power-Down & Reset Timing
PDN Pulse Width
PDN Reject Pulse Width
PDN “” to SDTO valid
(Note 10) tPD
150
(Note 10) tRPD
(Note 11) tPDV
4129
30
ns
ns
1/fs
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
Note 9. In the case of MCLK duty cycle is 50%.
Note 10. The AK5720 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L”
for more han 150ns for a certain reset. The AK5720 is not reset by the “L” pulse less than 30ns.
Note 11. This is the count of LRCK “↑” from the PDN pin = “H”.
MS1641-E-02
- 11 -
2014/12