AK5720 Datasheet, PDF (12/25 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ADC

■ Timing Diagram
MCLK
LRCK
BICK
MCLK
LRCK
BICK
[AK5720]
1/fCLK
VIH
VIL
tCLKH
tCLKL
1/fs
VIH
VIL
tLRH
tLRL
tBCK
VIH
VIL
tBCKH
tBCKL
Figure 1. Clock Timing (Slave mode)
1/fCLK
VIH
VIL
tCLKH
tCLKL
1/fs
tLRH
50%VD
1/fBCK
50%VD
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 2. Clock Timing (Master mode)
MS1641-E-02
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2014/12