AK5720 Datasheet, PDF (16/25 Pages) Asahi Kasei Microsystems – 96kHz 24-Bit ADC

[AK5720]
■ System Clock
13. Functional Descriptions
MCLK, BICK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized
with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency
and the system clock frequency. All external clocks (MCLK, BICK and LRCK) must be present unless PDN
pin = “L”. If the external clocks are not present, place the AK5720 in power-down mode (PDN pin = “L”). In
master mode, the master clock (MCLK) must be provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
96kHz
MCLK
128fs
N/A
N/A
N/A
N/A
192fs
N/A
N/A
N/A
N/A
256fs
384fs
8.192MHz 12.288MHz
11.2896MHz 16.9344MHz
12.288MHz 18.432MHz
24.576MHz 36.864MHz
Table 1. System Clock Example
512fs
16.384MHz
22.5792MHz
24.576MHz
N/A
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
■ Audio Interface Format
MCLK frequency, the relationship of BICK frequency and fs, and master/slave mode are set by external
resistance value of the CKS pin and the CKS pin connection as shown in Table 2.
When the CKS pin is connected to GND or VA directly, or via an external 4.7kΩ resistor (Normal mode), the
DIF/TDMI pin becomes an audio data format select pin. Two kinds of data formats: 24bit MSB justified and
I²S formats can be chosen by the DIF pin. The audio data is output on the falling edge of BICK from the SDTO
pin. The audio interface supports both master and slave modes. In master mode, BICK and LRCK are output
and they are input in slave mode. In master mode, LRCK frequency is fixed to 1fs and the BICK frequency is
fixed to 64fs.
When the CKS pin is connected to GND or the VA pin via an external resistor of 18kΩ or 82kΩ (TDM mode),
the DIF/TDMI pin becomes a TDM data input pin. In TDM mode, the audio data is output on a rising edge of
BICK from the SDTO pin. When inputting the SDTO output data to the TDMI pin, this SDTO data has a delay
which fills set-up or hold time of BICK rising .
Mode
0
1
2
3
4
Normal
5
6
7
8
9
10
TDM
11
CKS
< 10Ω to GND
(Short to GND)
< 10Ω to VA
(Short to VA)
4.7kΩ±10% to
GND
4.7kΩ±10% to VA
18kΩ±10% to GND
18kΩ±10% to VA
82kΩ±10% to GND
82kΩ±10% to VA
DIF
/TDMI
SDTO
Master
/Slave
MCLK
L
H
MSB
I²S
Slave
256/384fs (8kfs96k)
512/768fs (8kfs48k)
L
H
MSB
I²S
Master
256fs (8kfs96k)
L
H
MSB
I²S
Master
384fs (8kfs96k)
L
H
MSB
I²S
Master
512fs (8kfs48k)
TDMI MSB Master 256fs (8kfs96k)
TDMI
TDMI
TDMI
MSB
I²S
I²S
Slave
Master
Slave
256fs (8kfs96k)
256fs (8kfs96k)
256fs (8kfs96k)
Table 2. Operation Mode Select
LRCK
H/L
L/H
H/L
L/H
H/L
L/H
H/L
L/H




BICK
 48fs or
32fs
64fs
64fs
64fs
256fs
256fs
256fs
256fs
Note 12. SDTO outputs 16-bit data when BICK=32fs.
MS1641-E-02
- 16 -
2014/12