AK4543 Datasheet, PDF (15/31 Pages) Asahi Kasei Microsystems – AC’97 Rev 2.1 Multimedia Audio CODEC

[ASAHI KASEI]
[AK4543]
nAC-link Input Frame(SDATA_IN)
Each AC-link frame consists of one 16bit tag phase and twelve 20bit slots used for data and control.
a) Slot0
Slot0 is a special frame, and consists of 16bit s. Slot0 is also called the “Tag phase”. The AK4543 supports bits
15-11 and bits1-0. Each bit indicates “1”=valid(normal operation) or ready, “0”=invalid(abnormal operation) or not
ready.
If the first bit in the slot 0 is valid, the AK4543 is ready for normal operation. ³If the “Codec Ready” bit is invalid,
the following bits and remaining slots are all “0”. The AC’97 controller should ignore the following bits in the slot
0 and all other slots.
Bit 14 means that Slot 1(Status Address) output is valid or invalid. And Bit 13 means that Slot 2(Status Data ) is
valid or invalid.
The following table shows the relationship between Bit 14,13 and each Status of the AK4543.
Bit 15
Bit 14
Bit 13
Status
(CodecReady) (StatusAddress) (StatusData)
1
1
1
There is a Read Command in the previous frame.
Then both Slot 1 and Slot 2 output normal data.
If the access to non-implemented register or odd register is requested, the AK4543
returns “valid 7-bit register address in slot 1 and returns “valid”0000h data in slot
2 on the next AC-link frame.
1
1
0
Prohibited or non-existing
1
0
0
There is no Read Command in the previous frame. Both Slot 1 and Slot 2 output
All”0”.
1
0
1
Prohibited or non-existing
Note 1). The above Read sequence is done as response for previous frames read command. That is, if the previous
frame is a Write Command, AK4543 outputs bit1 4 =”0”, bit13 =”0” and slot 1&2 = All”0”.
Bit12 means the output of Slot 3( PCM(ADC) Left) is valid or invalid. And Bit 11 means the output of Slot
4(PCM(ADC)Left) is valid or invalid. Bits10-0 are filled with “0”.
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the
immediately following falling edge of BIT_CLK, the AK4543 samples the assertion of SYNC. This falling edge marks the time when
both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AK4543 transitions SDATA_IN
into the first bit position of slot 0 (“Codec Ready” bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and
subsequently sampled by the AC ’97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions,
and subsequent sample points for both incoming and outgoing data streams are time aligned.
SYNC
BIT_CLK
SDATA_IN
Codec
Ready
Slot1 Slot2 Slot3
Slot4 Slot5
Slot6
Slot7
Slot8
“1/0” “1/0” “1/0” “1/0” “1/0” “0” “0” “0” “0”
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7
Slot 0
Slot11 Slot12
“0” “0” “0” “0” “0”
Bit4 Bit3 Bit2 Bit1 Bit0
Slot 1
b) Slot1
Status Address Port
Audio input frame slot1’s stream echoes the control register index, for historical reference, for the data to be returned in slot2.
(Assuming that slots1 valid bit and slot2 valid bit in the slot0 had been tagged “valid” by the AK4543)
BIT_CLK
SDATA_IN
Slot 0
Bit19 Bit18 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit9 Bit2 Bit1 Bit0 Bit19 Bit18 Bit17 Bit16
“0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “1/0” “0” “0” “0” “0” “0” “0” “0”
Slot 1
Status Address Port
Slot 2
3 _{When the AC’97 is not ready for normal operation, output bits are not specified in this documents and should be considered as}
invalid.
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1999/01