AK4543 Datasheet, PDF (12/31 Pages) Asahi Kasei Microsystems – AC’97 Rev 2.1 Multimedia Audio CODEC

[ASAHI KASEI]
[AK4543]
Slot
0
1
2
3
4
5
6
7
8
9
10
11
12
SYNC
Codec ID1:Codec ID0=0:0 or 0:1
SDATA
TAG Command Command PCM(dac) PCM(dac) All
All
All
All
All
All
All
All
OUT
Address Data
Left
Right
“0”
“0”
”0”
“0”
“0”
“0”
“0”
“0”
Codec ID1:Codec ID0=1:0
TAG Command Command All
All
All
All PCM(dac) PCM(dac)
All
All
All
All
Address Data
“0”
“0”
“0”
“0”
Left
Right
“0”
“0”
“0”
“0”
Codec ID1:Codec ID0=1:1
TAG Command Command All
All
All PCM(dac)
All
All PCM(dac) All
All
All
Address Data
“0”
“0”
“0”
Left
”0”
“0”
Right
“0”
“0”
“0”
SDATA
TAG
Status Status PCM(adc) PCM(adc) All
All
All
All
All
All
All
All
IN
Address Data
Left
Right
“0”
“0”
”0”
“0”
“0”
“0”
“0”
“0”
Tag Phase
Data Phase
48kHz
AC-link protocol identifies 13slots of data per frame. The frequency of sync is fixed to 48kHz. Only Slot 0, which is
the Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.
AC-link Audio Output Frame (SDATA_OUT)
a)Slot 0
Primary codec (Codec ID1: Codec ID0 = 0 : 0)
SYNC
BIT_CLK
SDATA_OUT
Valid
Frame
Slot1 Slot2 Slot3
Slot4 Slot5 Slot6
Slot7 Slot8
Slot9
Slot10 Slot11 Slot12
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9” Bit8 Bit7” Bit6” Bit5” Bit4 Bit3 Bit2 Bit1 Bit0
“1/0” “1/0” “1/0” “1/0” “1/0” “0” “0” “0” “0” “0” “0” “0” “0” “0” “0” “0”
1 BIT_CLK delay
Slot 0
Slot 1
Secondary codec (Codec ID1 : Codec ID0 = 0 : 1 or 1 : 0 or 1 :1 )
SYNC
BIT_CLK
SDATA_OUT
1 BIT_CLK delay
Valid
Frame
Slot1 Slot2 Slot3
Slot4 Slot5 Slot6
Slot7 Slot8
Slot9
Slot10 Slot11 Slot12
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9” Bit8 Bit7” Bit6” Bit5” Bit4 Bit3 Bit2
“1/0” “0” “0” “1/0” “1/0” “0” “1/0” “1/0” “1/0” “1/0” “0” “0” “0” “0”
Slot 0
Bit1 Bit0
“1/0” “1/0”
Slot 1
The AK4543 checks bit15 (valid frame bit). Note that when the valid frame bit is “1”, at least one bit14-6 (slot 1-
9) or bit1-0 must be valid, bit5-2 will be “0”and should be ignored.
If bit15 is “0”, the AK4543 ignores all following information in the frame.
The AK4543 then checks the validity of each bit in the TAG phase (slot 0).
If each bit is “0”, the AK4543 ignores the slot indicated by “0”. On the other hand, if each bit is “1”, the slot is valid.
All bits in slot10-12(bit5-3) are “0” and bit2 is also “0”.
The AK4543 monitors bit1 and 0, which are codec ID configuration bits used in multiple codec implementations.
These bits are used to identify which codec the frame data is issued to.
<M0046-E-01>
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1999/01