AK4141 Datasheet, PDF (11/96 Pages) Asahi Kasei Microsystems – NICAM/A2/EIA-J Digital Stereo Decoder

[AK4141]
スイッチング特性 (Continued)
(Ta=-20 85C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;
C_L=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
LRCK Timing (Slave Mode)
Normal mode (TDM=“0”)
LRCK Frequency
Duty Cycle
fs
32
Duty
45
48
kHz
55
%
TDM256 mode (TDM=“1”)
LRCK Frequency
“H” time
“L” time
fs
tLRH
tLRL
32
1/256fs
1/256fs
48
kHz
ns
ns
SRC Input
LRCK Frequency
Duty Cycle
fs
8
Duty
45
192
KHz
55
%
LRCK Timing (Master Mode)
Normal mode (TDM=“0”)
LRCK Frequency
Duty Cycle
fs
32
48
kHz
Duty
50
%
TDM256 mode (TDM=“1”)
LRCK Frequency
fs
32
48
kHz
“H” time
(Note 7)
tLRH
1/8fs
ns
Audio Interface Timing (Slave mode)
Normal mode (TDM=“0”)
SCLK Period
tBCK
160
SCLK Pulse Width Low
tBCKL
65
Pulse Width High
tBCKH
65
LRCK Edge to SCLK “”
(Note 9) tLRB
30
SCLK “” to LRCK Edge
(Note 9) tBLR
30
LRCK to SDTO(MSB) (Except I²S mode)
tLRS
SCLK “” to SDTO
tBSD
SDTI Hold Time
tSDH
10
SDTI Setup Time
tSDS
10
ns
ns
ns
ns
ns
35
ns
35
ns
ns
ns
TDM256 mode (TDM=“1”)
SCLK Period
tBCK
81
SCLK Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK Edge to SCLK “”
(Note 9) tLRB
20
SCLK “” to LRCK Edge
(Note 9) tBLR
20
SCLK “” to SDTO
tBSD
TDMIN Hold Time
tSDH
10
TDMIN Setup Time
tSDS
10
ns
ns
ns
ns
ns
20
ns
ns
ns
SRC Input (Note 10)
SCLK Period
tBCK
81
ns
SCLK Pulse Width Low
tBCKL
32
ns
Pulse Width High
tBCKH
32
ns
LRCK Edge to SCLK “”
(Note 9)
tLRB
20
ns
SCLK “” to LRCK Edge
(Note 9)
tBLR
20
ns
SDTI Hold Time
tSDH
10
ns
SDTI Setup Time
tSDS
10
ns
MS0952-J-03
- 11 -
2013/12