TSI-4 Datasheet, PDF (57/61 Pages) Agere Systems – 4k x 4k Time-Slot Interchanger

Data Sheet, Revision 3
September 21, 2005
TSI-4
4k x 4k Time-Slot Interchanger
Table 7-8. Wide_Mode_Control (Read/Write)
For applications that require switching of time slots of greater than 8 bits, parallel devices must be used. These bits can be
used to facilitate such operation. Please contact your FAE if setting these bits to other than the default value of 0.
Address
0x0114E
Bit
Name/Description
Default
15:3 Unused.
—
2:0 Wide_Mode_Operation.
000
000 = Disable multifabric synchronization (i.e., normal mode) (default).
001 = Software algorithm mode, maximum allowable receive delay of approximately 7 µs.
010 = Software algorithm mode, maximum allowable receive delay of approximately 15 µs.
011 = Software algorithm mode, maximum allowable receive delay of approximately 31 µs.
100 = Disable multifabric synchronization (i.e., normal mode).
101 = Minimal latency mode, maximum allowable receive delay of approximately 7 µs.
110 = Minimal latency mode, maximum allowable receive delay of approximately 15 µs.
111 = Minimal latency mode, maximum allowable receive delay of approximately 31 µs.
Note: For the last three modes, the minimum, average, and maximum delay in low-latency
(LL) mode will be up to 7 µs, 15 µs, and 31 µs larger than regular LL mode. For the
software modes, the minimum delay in LL mode will be up to 7 µs, 15 µs, and 31 µs
larger, and the maximum delay will be up to 132 µs, 140 µs, and 156 µs larger than
regular mode.
Agere Systems Inc.
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