TSI-4 Datasheet, PDF (36/61 Pages) Agere Systems – 4k x 4k Time-Slot Interchanger

TSI-4
4k x 4k Time-Slot Interchanger
Data Sheet, Revision 3
September 21, 2005
Table 6-13. CPU_Access_Error (CORWN)
Address
0x00008
Bit
Name/Description
Default
15:4 Unused.
—
3 PLL_Lock_Error. This bit indicates if the device's master PLL is locked to the incoming CHI —
reference clock (CHICLK).
0 = Locked.
1 = Not locked.
2 Access_Time_Out_Error.
—
0 = No time-out.
1 = Indicates that a time-out has occurred internal to the TFRA84J13 device on a
microprocessor access.
1 Invalid_Address_Error.
—
0 = No invalid address.
1 = Indicates that a microprocessor access to an invalid address has occurred. The address
causing this error can be found in the Invalid_Address_Trap register (see Table 6-18 on
page 38).
0 Data_Parity_Error.
—
0 = No data parity error.
1 = Indicates that a microprocessor data bus parity error has occurred.
Table 6-14. CPU_Access_Error_Mask (Read/Write)
Address
0x0000A
Bit
Name/Description
15:4 Unused.
3 PLL_Lock_Error_Mask.
0 = The PLL_Lock_Error bit (see Table 6-13) will cause an interrupt if active.
1 = The PLL_Lock_Error bit is blocked from causing an interrupt.
2 Access_Time-out_Error_Mask.
0 = The Access_Time_Out_Error bit (see Table 6-13) will cause an interrupt if active.
1 = The Access_Time_Out_Error bit is blocked from causing an interrupt.
1 Invalid_Address_Error_Mask.
0 = The Invalid_Address_Error bit will (see Table 6-13) cause an interrupt if active.
1 = The Invalid_Address_Error bit is blocked from causing an interrupt.
0 Data_Parity_Error_Mask.
0 = The Data_Parity_Error bit will (see Table 6-13) cause an interrupt if active.
1 = The Data_Parity_Error bit is blocked from causing an interrupt.
Default
—
1
1
1
1
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