TSI-4 Datasheet, PDF (31/61 Pages) Agere Systems – 4k x 4k Time-Slot Interchanger

Data Sheet, Revision 3
September 21, 2005
TSI-4
4k x 4k Time-Slot Interchanger
6 Register Description
This section describes the purpose and operation of each register bit, its dependencies, and its initial state.
6.1 Device Addressing Notes
All device addresses shown are physical byte offset addresses in the microprocessor space, not the actual addresses in the
device itself. The device uses 2¹⁷ bytes of address spectrum.
The following assumptions are made:
„ The device is connected to the microprocessor as a 16-bit word accessed device (not byte addressable), with ADDR[00]
connected to address bit 1 of the microprocessor.
„ The microprocessor’s address bit 0 (high/low byte) is not used by the device.
Note: All addresses are expressed in hexadecimal. Unless otherwise indicated by a 0x, register bit states (in default states)
are expressed in binary.
6.2 Acronyms Used
„ CS—Connection store.
„ CSG—Connection store generator.
„ PLL—Phase-locked loop.
„ SF—Switch fabric.
„ TPG—Test pattern generator.
„ TPM—Test pattern monitor.
„ VCO—Voltage-controlled oscillator.
6.3 Address Map
Table 6-1. Address Map
Register Groups
Global Control
Connection Store Generator
Test Pattern Generator and Monitor
Reserved
CHI Control
Switch Fabric Control
Reserved
Reserved
Connection Store
Reserved
Address Space (Words)
512
256
256
256
896
1,920
4,096
24,576
16,364
16,324
Address Range
0x00000—0x003FE
0x00400—0x005FE
0x00600—0x007FE
0x00800—0x009FE
0x00A00—0x010FE
0x01100—0x01FFE
0x02000—0x03FFE
0x04000—0x0FFFE
0x10000—0x17FFE
0x18000—0x1FFFE
Note: The address space is expressed in decimal. Because ADDR[00] on the device is connected to ADDR[01] on the mi-
croprocessor, the device only occupies even addresses in the microprocessor address space.
Agere Systems Inc.
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