TSI-4 Datasheet, PDF (23/61 Pages) Agere Systems – 4k x 4k Time-Slot Interchanger

Data Sheet, Revision 3
September 21, 2005
TSI-4
4k x 4k Time-Slot Interchanger
FSYNC
CHICLK
w/ 0 offset
TS127 B7
TS0 B0
TS0 B1
data sampled
TS0 B2
TS0 B3
TS0 B4
w/ ¼ bit offset
TS127 B7
TS0 B0
TS0 B1
data sampled
TS0 B2
TS0 B3
TS0 B4
w/ ½ bit offset
TS127 B7
TS0 B0
TS0 B1
data sampled
TS0 B2
TS0 B3
w/ ¾ bit offset TS 127 B6
TS127 B7
TS0 B0
TS0 B1
data sampled
TS0 B2
TS0 B3
w/ bit offset = 1
TS127 B6
TS127 B7
TS0 B0
data sampled
TS0 B1
TS0 B2
TS0 B3
w/ 2¾ bit offset TS 127 B4
TS127 B5
TS127 B6
TS127 B7
data sampled
TS0 B0
TS0 B1
w/ bit offset = 7
TS127 B0
TS127 B1
TS127 B2
data sampled
TS127 B3
TS127 B4
TS127 B5
w/ TS offset = 1,
bit offset = 0
TS126 B7
TS127 B0
TS127 B1
data sampled
TS127 B2
TS127 B3
TS127 B4
w/ TS offset = 13,
bit offset = 3¼
TS114 B4
TS114 B5
TS114 B6
data sampled
TS114 B7
TS115 B0
TS115 B1
w/ TS offset = 127, TS 127 B7
bit offset = 7¾
TS0 B0
TS0 B1
TS0 B2
data sampled
TS0 B3
TS0 B4
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Figure 5-7. Typical Receive CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK
FSYNC
CHICLK
w/ 0 offset TS 127 B6
TS127 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
w/ ¼ bit offset
TS127 B6
TS127 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
w/ ½ bit offset
TS127 B6
TS127 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
w/ bit offset = 1 TS 127 B5
TS127 B6
TS127 B7
TS0 B0
TS0 B1
TS0 B2
w/ TS offset = 1, TS 126 B6
bit offset = 0
TS126 B7
TS127 B0
TS127 B1
TS127 B2
TS127 B3
w/ TS offset = 127,
bit offset = 7¾
TS127 B7
TS0 B0
TS0 B1
TS0 B2
TS0 B3
Note: For this timing diagram, it is assumed that FSYNC has been programmed to be active-high, and to be sampled by the rising edge of the CHICLK.
Figure 5-8. Transmit CHI Timing with 8.192 Mbits/s Data and 16.384 MHz CHICLK
Agere Systems Inc.
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