TSI-4 Datasheet, PDF (34/61 Pages) Agere Systems – 4k x 4k Time-Slot Interchanger

TSI-4
4k x 4k Time-Slot Interchanger
Data Sheet, Revision 3
September 21, 2005
Table 6-7. Connection Store
Address
0x10000—0x17FFC Low_Control_Word
0x10002—0x17FFE High_Control_Word
Register
Access Mode
Read/Write
Read/Write
Table 6-8. Reserved Registers
The following register will not cause an Invalid_Address_Error (see Table 6-13 on page 36) and are reserved.
Address
0x00016
Reserved_0
Register
Access Mode
Read/Write
6.5 Global Control Registers
The default field indicates the state of each register bit following a hardware or software reset cycle.
These registers are located at the top level of the design and are used to determine operations that affect more than one
block within the device. These could be registers required for control of the microprocessor port block or register functions
that are not naturally associated with other blocks. Global resets and output enables are included in this section.
Table 6-9. Version_Control (Read Only)
Address Bit
Name/Description
0x00000 15 Reserved.
14:12 Version_Number. TSI version number. TSI version register will change each time the
device is changed.
11:0 Agere_Systems_Identification_Number. This is the ID code assigned to Agere Systems
Inc. by the JTAG standards body.
Default
0
001
0x190
Table 6-10. Chip_Identity (Read Only)
Address Bit
Name/Description
0x00002 15:0 Chip_Identity. This register contains the unique identification code for the device.
Default
0x26D1
34
Agere Systems Inc.