ADSP-BF542_07 Datasheet, PDF (9/68 Pages) Analog Devices – Embedded Processor

Preliminary Technical Data
Table 4. System Interrupt Controller (SIC) (Continued)
Peripheral IRQ
(IRQ) Source
CAN0 Status IRQ
DMA18 IRQ (SPORT2 RX)
DMA19 IRQ (SPORT2 TX)
DMA20 IRQ (SPORT3 RX)
DMA21 IRQ (SPORT3 TX)
DMA13 IRQ (EPPI1)
DMA14 IRQ (EPPI2, Host DMA)
DMA5 IRQ (SPI1)
DMA23 IRQ (SPI2)
DMA8 IRQ (UART1 RX)
DMA9 IRQ (UART1 TX)
DMA10 IRQ (ATAPI RX)
DMA11 IRQ (ATAPI TX)
TWI0 IRQ
TWI1 IRQ
CAN0 Receive IRQ
CAN0 Transmit IRQ
MDMA Stream 2 IRQ
MDMA Stream 3 IRQ
MXVR Status IRQ
MXVR Control Message IRQ
MXVR Asynchronous Packet IRQ
EPPI1 Error IRQ
EPPI2 Error IRQ
UART3 Status IRQ
Host DMA Status
Reserved
Pixel Compositor (PIXC) Status IRQ
NFC Error IRQ
ATAPI Error IRQ
CAN1 Status IRQ
DMAR0 Block IRQ
DMAR1 Block IRQ
DMAR0 Overflow Error IRQ
DMAR1 Overflow Error IRQ
DMA15 IRQ (PIXC0)
DMA16 IRQ (PIXC1)
DMA17 IRQ (PIXC2)
DMA22 IRQ (SDH/NFC)
IRQ GP IRQ Core
ID (at Reset) IRQ ID
32 IVG7
0
33 IVG9
2
34 IVG9
2
35 IVG9
2
36 IVG9
2
37 IVG9
2
38 IVG9
2
39 IVG10
3
40 IVG10
3
41 IVG10
3
42 IVG10
3
43 IVG10
3
44 IVG10
3
45 IVG11
4
46 IVG11
4
47 IVG11
4
48 IVG11
4
49 IVG13
6
50 IVG13
6
51 IVG11
4
52 IVG11
4
53 IVG11
4
54 IVG7
0
55 IVG7
0
56 IVG7
0
57 IVG7
0
58 IVG7
0
59 IVG7
0
60 IVG7
0
61 IVG7
0
62 IVG7
0
63 IVG7
0
63 IVG7
0
63 IVG7
0
63 IVG7
0
64 IVG8
1
65 IVG8
1
66 IVG8
1
67 IVG8
1
ADSP-BF542/4/8/9
Table 4. System Interrupt Controller (SIC) (Continued)
Peripheral IRQ
(IRQ) Source
Counter (CNT) IRQ
Keypad (KEY) IRQ
CAN1 RX IRQ
CAN1 TX IRQ
SDH Mask 0 IRQ
SDH Mask 1 IRQ
Reserved
USB_INT0 IRQ
USB_INT1 IRQ
USB_INT2 IRQ
USB_DMAINT IRQ
OTPSEC IRQ
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Timer 0 IRQ
Timer 1 IRQ
Timer 2 IRQ
Timer 3 IRQ
Timer 4 IRQ
Timer 5 IRQ
Timer 6 IRQ
Timer 7 IRQ
Pin IRQ 2 (PINT2)
Pin IRQ 3 (PINT3)
IRQ GP IRQ Core
ID (at Reset) IRQ ID
68 IVG8
1
69 IVG8
1
70 IVG11
4
71 IVG11
4
72 IVG11
4
73 IVG11
4
74 IVG11
4
75 IVG11
4
76 IVG11
4
77 IVG11
4
78 IVG11
4
79 IVG11
4
80 IVG11
4
81 IVG11
4
82 IVG11
4
83 IVG11
4
84 IVG11
4
85 IVG11
4
86 IVG11
4
87 IVG11
4
88 IVG11
4
89 IVG11
4
90 IVG11
4
91 IVG11
4
92 IVG11
4
93 IVG11
4
94 IVG12
5
95 IVG12
5
Event Control
The ADSP-BF542/4/8/9 processor provides the user with a very
flexible mechanism to control the processing of events. In the
CEC, three registers are used to coordinate and control events.
Each register is 16 bits wide:
• CEC interrupt latch register (ILAT). The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
Rev. PrE | Page 9 of 68 | April 2007