ADSP-BF542_07 Datasheet, PDF (57/68 Pages) Analog Devices – Embedded Processor

Preliminary Technical Data
ADSP-BF542/4/8/9
JTAG Test And Emulation Port Timing
Table 47 and Figure 35 describe JTAG port operations.
Table 47. JTAG Port Timing
Parameter
Minimum Maximum Unit
Timing Parameters
t_TCK
TCK Period
t_STAP
TDI, TMS Setup Before TCK High
t_HTAP
TDI, TMS Hold After TCK High
t_SSYS
System Inputs Setup Before TCK High¹
t_HSYS
System Inputs Hold After TCK High¹
t_TRSTW
TRST Pulsewidth² (measured in TCK cycles)
Switching Characteristics
20
ns
4
ns
4
ns
4
ns
5
ns
4
TCK
t_DTDO
t_DSYS
TDO Delay from TCK Low
System Outputs Delay After TCK Low³
10
ns
0
12
ns
1 _{System Inputs=PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0, DQ15–0, DQS1–0, D15–0, ATAPI_PDIAG, CLKIN, RESET, NMI,}
BMODE3–0, MFS, MLF_P, and MLF_M.
2 _{50 MHz Maximum}
3 _{System Outputs=PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0, DQ15–0, DQS1–0, D15–0, DA12–0, DBA1–0, DQM1–0, DCLK2–1,}
DCLK2–1, DCS1–0, DCKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, EMU, CLKOUT, CLKBUF, EXT_WAKE.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t_TCK
t_STAP
t_HTAP
t_DTDO
t_SSYS
t_HSYS
t_DSYS
Figure 35. JTAG Port Timing
Rev. PrE | Page 57 of 68 | April 2007