ADSP-BF542_07 Datasheet, PDF (18/68 Pages) Analog Devices – Embedded Processor

ADSP-BF542/4/8/9
specified by the crystal manufacturer. System designs should
verify the customized values based on careful investigations on
multiple devices over temperature range.
CLKOUT
CLKBUF
BLACKFIN
TO PLL CIRCUITRY
EN
EN
CLKIN
330⍀*
XTAL
FOR OVERTONE
OPERATION ONLY:
18 pF*
18 pF*
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Figure 6. External Crystal Connections
A third-overtone crystal can be used at frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 6. A design procedure for third-overtone oper-
ation is discussed in detail in application note EE-168.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 7 on Page 18, the core clock
(CCLK) and system peripheral clock (SCLK) are derived from
the input clock (CLKIN) signal. An on-chip PLL is capable of
multiplying the CLKIN signal by a programmable
1؋ to 63؋ multiplication factor (bounded by specified mini-
mum and maximum VCO frequencies). The default multiplier
is 10؋, but it can be modified by a software instruction
sequence. On-the-fly frequency changes can be effected by sim-
ply writing to the PLL_DIV register.
On-the-fly CCLK and SCLK frequency changes can be effected
by simply writing to the PLL_DIV register. Whereas the maxi-
mum allowed CCLK and SCLK rates depend on the applied
voltages V_DDINT and V_DDEXT, the VCO is always permitted to run
up to the frequency specified by the part’s speed grade. The
CLKOUT pin reflects the SCLK frequency to the off-chip world.
Preliminary Technical Data
It functions as reference for many timing specifications. While
inactive by default, it can be enabled using the EBIU_SDGCTL
and EBIU_AMGCTL registers.
DYNAMIC MODIFICATION
REQUIRES PLL SEQUENCING
DYNAMIC MODIFICATION
ON-THE-FLY
CLKI N
PLL
0.5x - 64x
VCO
، 1, 2, 4, 8
، 1:15
CCLK
S CLK
SCLK Յ CCLK/2
SCLK Յ 133MHz
Figure 7. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are two
through 15. Table 7 illustrates typical system clock ratios. The
default ratio is 5.
Table 7. Example System Clock Ratios
Signal Name
SSEL3–0
0010
0110
1010
Example Frequency Ratios
Divider Ratio ^(MHz)
VCO/SCLK VCO
SCLK
2:1
200
100
6:1
300
50
10:1
500
50
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f_SCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. The default ratio is 1. This programmable core clock
capability is useful for fast core frequency modifications.
Rev. PrE | Page 18 of 68 | April 2007