ADSP-BF542_07 Datasheet, PDF (42/68 Pages) Analog Devices – Embedded Processor

ADSP-BF542/4/8/9
Preliminary Technical Data
External Port Bus Request and Grant Cycle Timing
Table 29 and Table 30 on Page 43 and Figure 19 and Figure 20
on Page 43 describe external port bus request and grant cycle
operations for synchronous and for asynchronous BR.
Table 29. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Timing Requirements
t_BS
BR Setup to Falling Edge of CLKOUT
t_BH
Falling Edge of CLKOUT to BR Deasserted Hold Time
Switching Characteristics
t_SD
CLKOUT Low to xMS, Address, and RD/WR disable
t_SE
CLKOUT Low to xMS, Address, and RD/WR enable
t_DBG
CLKOUT High to BG High Setup
t_EBG
CLKOUT High to BG Deasserted Hold Time
t_DBH
CLKOUT High to BGH High Setup
t_EBH
CLKOUT High to BGH Deasserted Hold Time
Min
Max
Unit
4.0
ns
0.0
ns
4.5
ns
4.5
ns
3.6
ns
3.6
ns
3.6
ns
3.6
ns
CLKOUT
BR
AMSx
ADDR19-1
ABE1-0
AWE
ARE
BG
BGH
t_BS
t_BH
t_SD
t_SD
t_SD
t_DBG
t_DBH
Figure 19. External Port Bus Request and Grant Cycle Timing with Synchronous BR
t_SE
t_SE
t_SE
t_EBG
t_EBH
Rev. PrE | Page 42 of 68 | April 2007