ADSP-BF542_07 Datasheet, PDF(21/68 Page) Analog Devices

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ADSP-BF542_07 Datasheet, PDF (21/68 Pages) Analog Devices – Embedded Processor

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Preliminary Technical Data

ADSP-BF542/4/8/9

The assembly language, which takes advantage of the proces-

sorâs unique architecture, offers the following advantages:

â¢ Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

â¢ A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

â¢ All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

â¢ Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

â¢ Code density enhancements, which include intermixing of

16- and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded in

16 bits.

DEVELOPMENT TOOLS

The ADSP-BF542/4/8/9 processor is supported with a complete

set of CROSSCOREÂ® software and hardware development tools,

including Analog Devices emulators and VisualDSP++Â® devel-

opment environment. The same emulator hardware that

supports other Blackfin processors also fully emulates the

ADSP-BF542/4/8/9 processor.

EZ-KIT LiteÂ® Evaluation Board

For evaluation of ADSP-BF542/4/8/9 processors, use the ADSP-

BF548 EZ-KIT Lite board available from Analog Devices. Order

part number ADDS-BF548-EZLITE. The board comes with on-

chip emulation capabilities and is equipped to enable software

development. Multiple daughter cards are available.

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every sys-

tem developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG processor. The emulator

uses the TAP to access the internal features of the processor,

allowing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor

system is set running at full speed with no impact on system

timing.

To use these emulators, the target board must include a header

that connects the processorâs JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see Analog Devices JTAG Emulation Technical Reference

(EE-68) on the Analog Devices web site under

www.analog.com/ee-notes. This document is updated regularly

to keep pace with improvements to emulator support.