EVAL-AD1871EBZ Datasheet, PDF (8/28 Pages) Analog Devices – Stereo Audio, 24-Bit, 96 kHz, Multibit
- ADC

AD1871
CONTROL INTERFACE (SPI) TIMING
Mnemonic
t_CCH
t_CCL
t_CCP
t_CDS
t_CDH
t_CLS
t_CLH
t_COE
t_COD
t_COTS
Description
CCLK High Width
CCLK Low Width
CCLK Period
CDATA Setup Time
CDATA Hold Time
CLATCH Setup Time
CLATCH Hold Time
COUT Enable
COUT Delay
COUT Three-State
Min
Typ
Max Unit Comment
40
ns
40
ns
80
ns
10
ns
To CCLK Rising
10
ns
From CCLK Rising
10
ns
To CCLK Rising
10
ns
From CCLK Rising
15
ns
From CLATCH Falling
20
ns
From CCLK Falling
25
ns
From CLATCH Rising
CCLK
CLATCH
CIN
COUT
t_CCH
t_CCL
t_CCL
t_CSU
D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
t_CHD
D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
t_CLH
Figure 7. Control Interface Timing
DIGITAL I/O
Parameter
Input Voltage High (V_IH)
Input Voltage Low (V_IL)
Input Leakage (I_IH @ V_IH = 5 V)
Input Leakage (I_IL @ V_IL = 0 V)
Output Voltage High (V_OH @ I_OH = –2 mA)
Output Voltage Low (V_OL @ I_OL = +2 mA)
Input Capacitance
Min
Typ
2.4
ODVDD – 0.4 V
POWER
Parameter
Min
Typ
Supplies
Voltage, AVDD, and DVDD
4.5
5
Voltage, ODVDD
2.7
Analog Current
40
Analog Current—Power-Down (MCLK Running)
4.0
Digital Current, DVDD
18
Digital Current, ODVDD
0.5
Digital Current—Power-Down (MCLK Running) DVDD*
0.8
Digital Current—Power-Down (MCLK Running) ODVDD*
1.0
Power Supply Rejection
1 kHz 300 mV p-p Signal at Analog Supply Pins
–86
20 kHz 300 mV p-p Signal at Analog Supply Pins
–77
*RESET held low.
TEMPERATURE RANGE
Parameter
Specifications Guaranteed
Functionality Guaranteed
Storage
Min
Typ
25
–40
–65
Specifications subject to change without notice.
Max
0.8
10
10
0.4
15
Max
5.5
5.5
45
6.0
22
1.0
2.0
15.0
Max
+105
+150
–8–
Unit
V
V
mA
mA
V
V
pF
Unit
V
V
mA
mA
mA
mA
mA
mA
dB
dB
Unit
∞C
∞C
∞C
REV. 0