EVAL-AD1871EBZ Datasheet, PDF (16/28 Pages) Analog Devices – Stereo Audio, 24-Bit, 96 kHz, Multibit
- ADC

AD1871
FUNCTIONAL DESCRIPTION
Clocking Scheme
The MCLK pin is the input for the master clock frequency to
the device. Nominally the MCLK frequency will be 256 ¥ f_S for
correct operation of the device. However, if the user’s MCLK is
a multiple of 256 ¥ f_S (perhaps 512 ¥ f_S or 768 ¥ f_S), it is possible
to divide down the MCLK frequency to a suitable internal master
clock frequency (IMCLK) using the MCLK divider block as
AMC BIT
(CONT REG I)
0/1
shown in Figure 8. The divide options can be chosen from pass-
through (/1), /2, or /3 corresponding with 256 ¥ f_S, 512 ¥ f_S, or
768 ¥ f_S MCLKs, respectively. The MCLK divider can be con-
trolled using the MCD1–MCD0 Bits of Control Register III.
(see Table XIII.)
The resulting internal MCLK (IMCLK) is used to run the
decimating and filtering engine and must be chosen to be at a
ratio of 256 ¥ f_S.
HPE BIT
(CONT REG I)
ANALOG
INPUT
⌺-⌬
6.144MHz
MODULATOR
MODCLK
6.144MHz
IMCLK
DIVIDER
/2
/4
12.288MHz/
24.576MHz
IMCLK
MCLK
DIVIDER
/1 /2 /3
SINC
FILTER
384kHz/
768kHz
HALF-BAND
FILTERS
48kHz/
96kHz
HIGH-PASS
FILTERS
48kHz/
96kHz
MCLK
Figure 8. Clocking Scheme to Modulator and Filter Engine
Modulator
The AD1871’s analog ⌺-⌬ modulator section comprises a
second order multibit implementation using Analog Device’s
proprietary technology for best performance. As shown in
Figure 9, the two analog integrator blocks are followed by a
Flash ADC section that generates the multibit samples. The
output of the Flash ADC, which is thermometer encoded, is decoded
to binary for output to the filter sections and is scrambled for
feedback to the two integrator stages.
The modulator is optimized for operation at a sampling rate
of 6.144 MHz (which is 128 ¥ f_S at 48 kHz sampling and
64 ¥ f_S at 96 kHz sampling). The modulator clock control
(AMC Bit in Control Register I) is used to select the modulator
clock (MODCLK) as a ratio from the IMCLK. The modulator
clock divider options are /2 (default) for 48 kHz operation and
/4 for 96 kHz operation. When operating with an IMCLK of
12.288 MHz, the default divider setting (/2) gives a modulator clock
of 6.144 MHz. When operating with an IMCLK of 24.576 MHz,
the alternate divider setting (/4) gives a modulator clock of
6.144 MHz (see Figure 8).
If it is required to operate the device at a different output sample
rate than those detailed above, perhaps 44.1 kHz or 88.2 kHz,
the decimation filter cutoff characteristics can then be determined
from the normalized frequency response plot shown in TPC 6.
FROM
ANALOG
INPUT
͐
SECTION
͐
FLASH
ADC
THERMO-
METER
TO
BINARY
DECODER
DIGITAL
OUTPUT
(4 BITS/6.144MHz)
SCRAMBLER
FEEDBACK DACs
Figure 9. Modulator Block Diagram
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