EVAL-AD1871EBZ Datasheet, PDF (5/28 Pages) Analog Devices – Stereo Audio, 24-Bit, 96 kHz, Multibit
- ADC

DATA INTERFACE TIMING (STANDALONE MODE–MASTER)
Mnemonic
t_BDLY
t_BLDLY
t_BDDLY
Description
BCLK Delay
LRCLK Delay to Low
DOUT Delay
Min
Typ
Max
20
10
10
Unit
ns
ns
ns
Comment
From MCLK Rising
From BCLK Falling
From BCLK Falling
AD1871
MCLK
t_BDLY
BCLK
t_BLDLY
LRCLK
DOUT
LEFT-JUSTIFIED
MODE
t_BDDLY
MSB
MSB–1
DOUT
I²S-JUSTIFIED
MODE
MSB
DOUT
RIGHT-JUSTIFIED
MODE
MSB
LSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Master Data Interface Timing
REV. 0
–5–