EVAL-AD1871EBZ Datasheet, PDF (6/28 Pages) Analog Devices – Stereo Audio, 24-Bit, 96 kHz, Multibit
- ADC

AD1871
DATA INTERFACE TIMING (STANDALONE MODE–SLAVE)
Mnemonic
t_BCH
t_BCL
t_BDSD
t_LRS
t_LRH
Description
BCLK High Width
BCLK Low Width
DOUT Delay
LRCLK Setup
LRCLK Hold
Min
Typ
30
30
20
10
5
BCLK
LRCLK
DOUT
LEFT-JUSTIFIED
MODE
t_BCH
t_LRS
t_DBP
t_BCL
t_BDSD
MSB
MSB–1
Max
Unit
ns
ns
ns
ns
ns
DOUT
I²S-JUSTIFIED
MODE
MSB
DOUT
RIGHT-JUSTIFIED
MODE
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 3. Slave Data Interface Timing
Comment
From BCLK Falling
To BCLK Rising
From BCLK Rising
LSB
–6–
REV. 0