EVAL-AD1871EBZ Datasheet, PDF (7/28 Pages) Analog Devices – Stereo Audio, 24-Bit, 96 kHz, Multibit
- ADC

DATA INTERFACE TIMING (CASCADE MODE–MASTER)
Mnemonic
t_BCHDC
t_BCLDC
t_BLRDC
t_BDDC
t_BDIS
t_BDIH
Description
BCLK High Delay
BCLK Low Delay
LRCLK Delay
DOUT Delay
DIN Setup
DIN Hold
Min
Typ
20
20
10
10
10
10
Max
Unit
ns
ns
ns
ns
ns
ns
AD1871
Comment
From MCLK Rising
From MCLK Falling
From BCLK Rising
From BCLK Rising
To BCLK Rising
From BCLK Rising
MCLK
LRCLK
BCLK
DOUT
t_BCHDC
t_BCLDC
t_BLRDC
t_BDDC
Figure 4. Master Cascade Interface Timing
DATA INTERFACE TIMING (CASCADE MODE–SLAVE)
Mnemonic
t_BCHC
t_BCLC
t_BDSDC
t_LRSC
t_LRHC
t_BDIS
t_BDIH
Description
BCLK High Width
BCLK Low Width
DOUT Delay
LRCLK Setup
LRCLK Hold
DIN Setup
DIN Hold
Min
Typ
30
30
20
10
5
10
10
Max
Unit
ns
ns
ns
ns
ns
ns
ns
Comment
From BCLK Rising
To BCLK Rising
From BCLK Rising
To BCLK Rising
From BCLK Rising
LRCLK
BCLK
DOUT
t_LRHC
t_LRSC
t_BDSDC
t_BCHC
t_BCLC
Figure 5. Slave Cascade Interface Timing
DATA INTERFACE TIMING (MODULATOR MODE)
Mnemonic
Description
Min
t_MOCH
t_MOCL
t_MHDD
t_MLDD
t_MMDR
t_MMDF
MODCLK High Width
MODCLK Low Width
MOD DATA High Delay
MOD DATA Low Delay
MODCLK Delay Rising
MODCLK Delay Falling
Typ
MCLK
MCLK
30
20
30
20
Max
Unit
ns
ns
ns
ns
ns
ns
Comment
From MCLK Rising
From MCLK Falling
MCLK Falling to MODCLK Rising
MCLK Falling to MODCLK Falling
REV. 0
MODCLK
D[0– 3]
t_MHDD
t_MLDD
t_MOCH
t_MOCL
Figure 6. Modulator Mode Timing
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