ADP1823 Datasheet, PDF (8/32 Pages) Analog Devices – Dual, Interleaved, Step-Down DC-to-DC Controller with Tracking

ADP1823
Pin No.
26
27
28
29
30
31
32
Mnemonic
EN2
LDOSD
IN
VREG
SS1
TRK1
COMP1
Description
Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off.
Enabling starts the internal LDO. Tie to IN for automatic startup.
LDO Shut-Down Input. Only used to shut down the LDO in those applications where IN is tied directly to VREG.
Otherwise connect LDOSD to GND or leave it open, as it has an internal 100 kΩ pull-down resistor.
Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1823 from the LDO.
For input voltages between 2.9 V and 5.5 V, tie IN to VREG and PV.
Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG.
Bypass VREG to ground plane with 1 μF ceramic capacitor.
Soft Start Control Input. Connect a capacitor from SS1 to GND to set the soft start period.
Tracking Input for Channel 1. To track a master voltage, drive TRK1 from a voltage divider to the master voltage.
If the tracking function is not used, connect TRK1 to VREG.
Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to FB1 to compensate Channel 1.
Rev. A | Page 8 of 32